configureDACTileClock

Configure output clock frequency of DAC tile

Syntax

configureDACTileClock(rfDataConverter,tileId,resampleFactor)

Description

Add-On Required: This feature requires the HDL Coder Support Package for AMD FPGA and SoC Devices add-on.

configureDACTileClock(rfDataConverter,tileId,resampleFactor) configures the frequency of the output clock of the specified DAC tile for the provided resample factor.

Input Arguments

rfDataConverter — RF data converter

soc.RFDataConverter object

RF data converter, specified as an soc.RFDataConverter object. Via Ethernet, this object connects the host computer to the RF data converter on the connected SoC device. Use the object functions and properties of this object to configure the RF data converter.

tileId — Identifier of RF-DAC tile

0 | 1 | 2 | 3

Identifier of the RF-DAC tile connected to the programmable logic, specified as 0, 1, 2, or 3. Available options for the RF-DAC tile ID vary according to the specified RFSoC device. A tile contains several DACs, accessible as channels, and several shared timing units, including a clock and PLL.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

resampleFactor — Resample factor of shared clock for RF-DAC tile

nonnegative integer

Resample factor of the shared clock for the RF-DAC tile, specified as a nonnegative integer.

Data Types: double

Version History

Introduced in R2020b