Verification
Simulation and verification of generated HDL code using HDL test bench, cosimulation, or
FPGA-in-the-loop
You can verify the generated code by using HDL test bench, cosimulation (requires HDL Verifier™), or FPGA-in-the-loop (requires HDL Verifier).
FPGA-in-the-loop (FIL) simulation allows you to run a Simulink® or MATLAB® simulation with an FPGA board strictly synchronized with this software. When you use FIL in the Workflow Advisor, HDL Coder™ uses the loaded design to create the HDL code. See FPGA-in-the-Loop (HDL Verifier).
Topics
HDL Test Bench
- MATLAB Test Bench Requirements and Best Practices for Code Generation
What is a MATLAB test bench, requirements and best practices for HDL and High-Level Synthesis (HLS) code generation. - Specify Test Bench Clock Enable Toggle Rate
Specify test bench clock enable toggle rate. - Verify Code with HDL Test Bench
Simulate the generated HDL design under test (DUT) with test vectors from the test bench using the specified simulation tool. - Test Bench Generation
HDL Coder writes the DUT stimulus and reference data from your MATLAB or Simulink simulation to data files (.dat
).
Cosimulation
- Set Up for HDL Cosimulation (HDL Verifier)
To cosimulate your HDL code with a MATLAB or Simulink design, you must first: - Automatic Verification of Generated HDL Code from MATLAB (HDL Verifier)
Verify generated HDL code using a generated cosimulation script.
FPGA-in-the-Loop
- FPGA-in-the-Loop Simulation Workflows (HDL Verifier)
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
Troubleshooting
- Resolve Index Errors During Simulation
Troubleshoot index errors during HDL code simulation.
Related Information
- HDL Cosimulation (HDL Verifier)
- FPGA-in-the-Loop (HDL Verifier)
- FPGA Board Customization