Define Custom Board and Reference Design for Zynq Ultrascale+ MPSoC Workflow

This example shows how to define and register a custom board and reference design for the Zynq® workflow using a Xilinx® Zynq® UltraScale+ MPSoC ZCU104 evaluation kit. You can also define and register a custom board or a custom reference design for other Zynq UltraScale+ platforms.

Requirements

To run this example, you need:

• A Xilinx Vivado Design Suite. For a list of supported versions, see HDL Language Support and Supported Third-Party Tools and Hardware.

• A Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit.

• HDL Coder™ Support Package for Xilinx FPGA and SoC Devices.

Set Up the Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit

To familiarize yourself with the features of the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit, see the Xilinx Zynq Ultrascale+ MPSoC ZCU104 Evaluation Kit.

1. Set up the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit.

2. Install the USB COM port drivers on your computer.

3. Configure the board to boot in SD-boot mode by setting switch SW6 to these positions: 1-ON, 2-OFF, 3-OFF, and 4-OFF, as shown in the figure.

4. Connect the shared UART/JTAG USB port on the board to your computer.

5. Connect the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit to your computer by using an Ethernet cable. The default IP address of the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit is 192.168.1.101.

6. Download the ZCU104 MPSoC Linux image, extract the ZIP archive, and copy the contents to the microSD card. Insert the microSD card into connector J4.

7. Set up the Xilinx Vivado tool path using the hdlsetuptoolpath function.

hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2023.1\bin\vivado.bat');

Use your own Xilinx Vivado installation path when executing the command.

8. Set up the Zynq hardware connection using the xilinxsoc function.

h = xilinxsoc();

Create and Export Custom Reference Design Using Xilinx Vivado

A reference design captures the complete structure of an SoC design and defines the different components and their interconnections. Use the HDL Coder SoC workflow to generates an IP core that integrates with the reference design and program an SoC board. This figure shows the relationship between a reference design, an HDL IP core, and an SoC board.

To create and export a reference design by using the Xilinx Vivado IP Integrator tool environment, follow these steps.

1. Create an empty Xilinx Vivado RTL project by using the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit as the default board.

2. Create an empty block design and add the Zynq Ultrscale+ MPSoC Processing System IP block. Run the block automation to set a board preset for Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit, which contains the parameters for the Zynq Ultrascale+ MPSoC processing system.

The MIO peripherals are marked in accordance with the board definition as a result of applying a board preset.

3. Complete the block design.

This block design does not contain any information about the HDL IP core.

4. Export the completed block design as a TCL script named design_led.tcl, as shown in the figure.

The exported Tcl script constitutes the custom reference design. You use the Tcl script to recreate the block design and integrate the generated HDL IP core with the block design in a Xilinx Vivado project.

Register Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit in the HDL Workflow Advisor

To create the ZCU104 board in the HDL Workflow Advisor, follow these steps.

1. Create Board Registration File

Create a board registration file with the name hdlcoder_board_customization.m and add it to the MATLAB path. A board registration file contains a list of board plugins. A board plugin is a MATLAB package folder that contains the board definition file associated with that board. This code describes the contents of a board registration file that contains the board plugin ZCU104Registration, which registers the ZCU104 board in HDL Workflow Advisor.

function r = hdlcoder_board_customization
% Board plugin registration file
% 1. Any registration file with this name on MATLAB path will be picked up
% 2. Registration file returns a cell array pointing to the location of 
%    the board plug-ins
% 3. Board plugin must be a package folder accessible from MATLAB path,
%    and contains a board definition file

%   Copyright 2024 The MathWorks, Inc.

r = { ...
    'ZCU104Registration.plugin_board', ...
    };
end

2. Create Board Definition File

A board definition file contains information about the SoC board. This code describes the contents of the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit definition file plugin_board.m, which is in the board plugin folder ZCU104Registration. You can learn more about the FPFA I/O pin locations and standards in the ZCU104 master constraints file.

The BoardName property defines the name of the ZCU104 board as Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit in the HDL Workflow Advisor.

function hB = plugin_board()
% Board definition

% Construct board object
hB = hdlcoder.Board;
hB.BoardName    = 'Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit';

% FPGA device information
hB.FPGAVendor   = 'Xilinx';
hB.FPGAFamily   = 'Zynq UltraScale+';
hB.FPGADevice   = 'xczu7ev-ffvc1156-2-e';
hB.FPGAPackage  = '';
hB.FPGASpeed    = '';

% Tool information
hB.SupportedTool = {'Xilinx Vivado'};

% FPGA JTAG chain position
hB.JTAGChainPosition = 1;

% Add interfaces
% Standard "External Port" interface
hB.addExternalPortInterface( ...
    'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});

% Custom board external I/O interface
hB.addExternalIOInterface( ...
  'InterfaceID',    'LEDs General Purpose', ...
  'InterfaceType',  'OUT', ...
  'PortName',       'LEDs', ...
  'PortWidth',      4, ...
  'FPGAPin',        {'D5', 'D6', 'A5', 'B5'}, ...
  'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});

hB.addExternalIOInterface( ...
   'InterfaceID',    'Push Buttons', ...
   'InterfaceType',  'IN', ...
   'PortName',       'PushButtons', ...
   'PortWidth',      4, ...
   'FPGAPin',        {'B4', 'C4', 'B3', 'C3'}, ...
   'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});

hB.addExternalIOInterface( ...
   'InterfaceID',    'Slide switches ', ...
   'InterfaceType',  'IN', ...
   'PortName',       'SlideSwitches', ...
   'PortWidth',      4, ...
   'FPGAPin',        {'E4', 'D4', 'F5', 'F4'}, ...
   'IOPadConstraint', {'IOSTANDARD = LVCMOS33'});

Register Custom Reference Design in the HDL Workflow Advisor

To create and register the custom reference design in the HDL Workflow Advisor, follow these steps.

Create Reference Design Registration File

Create a reference design registration file named hdlcoder_ref_design_customization.m that contains a list of reference design plugins associated with the SoC board. A reference design plugin is a MATLAB package folder that contains the reference design definition file and all files associated with the SoC design project. A reference design registration file must also contain the name of the associated board.

This code describes the contents of a ZCU104 reference design registration file. This registration file contains the reference design plugin ZCU104Registration.Vivado2023_1, which is associated with the board Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit. HDL Coder now supports the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit with Xilinx Vivado tool version 2023.1. This creates a folder name that contains Vivado2023_1.

function [rd, boardName] = hdlcoder_ref_design_customization
% Reference design plugin registration file
% 1. The registration file with this name inside of a board plugin folder
%    will be picked up
% 2. Any registration file with this name on MATLAB path will also be picked up
% 3. The registration file returns a cell array pointing to the location of
%    the reference design plugins
% 4. The registration file also returns its associated board name
% 5. Reference design plugin must be a package folder accessible from
%    MATLAB path, and contains a reference design definition file
rd = {
	'ZCU104Registration.Vivado2023_1.plugin_rd', ...
     };
boardName = 'Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit';
end

Create Reference Design Definition File

A reference design definition file defines the interfaces between the custom reference design and the HDL IP core that is generated by the HDL Coder SoC workflow.

This code describes the contents of the ZCU104 reference design definition file plugin_rd.m, which is associated with the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit. The files in the reference design plugin file ZCU104Registration.Vivado2023_1. The ReferenceDesignName property defines the name of the reference design as Demo system in the HDL Workflow Advisor.

function hRD = plugin_rd()
% Reference design definition

%   Copyright 2024 The MathWorks, Inc.

% Construct reference design object
hRD = hdlcoder.ReferenceDesign('SynthesisTool', 'Xilinx Vivado');

hRD.ReferenceDesignName = 'Demo system';
hRD.BoardName = 'Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit';

% Tool information
hRD.SupportedToolVersion = {'2023.1'};

% add custom Vivado design
hRD.addCustomVivadoDesign( ...
    'CustomBlockDesignTcl', 'design_led.tcl', ...
    'VivadoBoardPart',      'xilinx.com:zcu104:part0:1.1');

% Add interfaces
% add clock interface
hRD.addClockInterface( ...
    'ClockConnection',   'clk_wiz_0/clk_out1', ...
    'ResetConnection',   'rst_clk_wiz_0_150M/peripheral_aresetn');

% add AXI4 and AXI4-Lite slave interfaces
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'axi_interconnect_0/M00_AXI', ...
    'BaseAddress',         '0x00A0000000', ...
    'MasterAddressSpace',  'zynq_ultra_ps_e_0/Data');

hRD.DeviceTreeName = 'system.dtb';

hRD.HasProcessingSystem= true;

% LocalWords:  devicetree axilite dtb

A reference design plugin must also contain the SoC design project files. The ZCU104 reference design plugin folder ZCU104Registration.Vivado2023_1 must contain the TCL script design_led.tcl that you export from the Xilinx Vivado project. The reference design definition file plugin_rd.m identifies the SoC design project file by using addCustomVivadoDesign function:

hRD.addCustomVivadoDesign('CustomBlockDesignTcl', 'design_led.tcl');

The reference design definition file also defines the interface connections between the custom reference design and the HDL IP core by using the addClockInterface and addAXI4SlaveInterface functions.

hRD.addClockInterface( ...
  'ClockConnection',   'core_clkwiz/clk_out1', ...
  'ResetConnection',   'sys_core_rstgen/peripheral_aresetn');
hRD.addAXI4SlaveInterface( ...
    'InterfaceConnection', 'axi_cpu_interconnect/M00_AXI', ...
    'BaseAddress',         '0x00A0000000', ...
    'MasterAddressSpace',  'sys_cpu/Data');

Note: The 'BaseAddress' of the AXI4 interface must be a valid address in the 'MasterAddressSpace'. The address must not create any address conflict with other address-based peripherals in the custom reference design.

Generate IP Core for ZCU104 Board

To generate an HDL IP core that blinks LEDs on the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit, use the custom board and reference design registration system.

1. Add the ZCU104 board registration file to the MATLAB path by using these commands:

example_root = (hdlcoder_amd_examples_root)
cd (example_root)
addpath(genpath('ZCU104'));

2. Open the Simulink LED blinking model.

open_system('hdlcoder_led_blinking_4bit');

3. Launch the HDL Workflow Advisor from the hdlcoder_led_blinking_4bit/led_counter subsystem by right-clicking the led_counter subsystem.

In the Set Target > Set Target Device and Synthesis Tool task, set Target workflow to IP Core Generation. In the Target Platform parameter, select Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit.

4. Click Run This Task.

5. In the Set Target > Set Target Reference Design task, set the Reference design to Demo system and click Run This Task.

6. In the Set Target Interface task, set the options in the Target Platform Interface column and click Run This Task.

7. To generate the IP core and view the IP core generation report, follow step 3 and step 4 of the Generate an HDL IP core using the HDL Workflow Advisor section in the Get Started with IP Core Generation from Simulink Model example.

8. To integrate the IP core into the reference design and create the Vivado project, follow step 1 of the Integrate the IP core with the Xilinx Vivado environment section in the Get Started with IP Core Generation from Simulink Model example.

9. After completing the Create Project task under Embedded System Integration, examine the Xilinx Vivado project. This figure shows the block design of the SoC project when you highlight the HDL IP core. Compare this block design with the block design you used to export the custom reference design to understand the relationship between the custom reference design and the HDL IP Core.

10. Follow steps 2, 3, and 4 of the Integrate the IP core with the Xilinx Vivado environment section in the Get Started with IP Core Generation from Simulink Model example to generate the software interface model, generate the FPGA bitstream, and program the target device, respectively.

11. After you load the bitstream, the LEDs on the Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation kit start blinking. You can control the LED blinking frequency and direction by executing the software interface model on the Zynq ARM processor. For more information, see the Generate a software interface model section in the Get Started with IP Core Generation from Simulink Model example.

See Also

• hdlsetuptoolpath

• Get Started with IP Core Generation from Simulink Model