When you enable speed and area optimizations that insert pipeline registers, use the clock-rate pipelining optimization to identify multicycle paths in your design. Clock-rate pipelining inserts pipeline registers at the faster clock rate, which improves clock frequency without introducing additional latency or by adding minimal latency.
Rationale for Clock-Rate Pipelining
The code generator introduces pipelines when you specify certain block implementations or enable some optimizations on the model, such as:
Multi-cycle block implementations
Input and output pipelining
Floating-point library mapping
Native floating-point HDL code generation
By default, in slow paths, these pipeline registers operate at the slow data rate. When you enable clock-rate pipelining, the pipeline registers operate at the faster clock rate. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.
How Clock-Rate Pipelining Works
The clock-rate pipelining optimization identifies slow paths or regions in the model by analyzing the block sample times. Blocks that have a sample time greater than the DUT base sample time are part of the slow path, and are potential candidates for clock-rate pipelining. In these slow paths, the code generator enables optimizations to introduce pipeline delays at the clock rate.
If you specify an Oversampling factor greater than one, the DUT sample time becomes slower than the actual clock rate. The code generator determines the maximum number of clock-rate pipelines that it can insert based on the DUT-to-block sample time ratio and the oversampling factor.
Maximum number of clock-rate delays = (block_rate
÷ DUT_base_rate) ×
Clock-rate pipelining identifies regions in the model that have the same slow data rate, and are delimited by either Delay blocks or blocks that introduce a rate transition. The code generator converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region. If the output of a clock-rate region is a Delay block at the data rate, HDL Coder™ absorbs that Delay block. To accommodate the delay, the code generator introduces several clock-rate pipelines corresponding to the ratio of the data rate to the clock rate.
HDL Coder generates a script that highlights blocks in your model that are
obstacles to clock-rate pipelining and a script to clear the highlighting.
Sometimes, if the code generator is unable to implement resource sharing or
streaming at the clock rate, it displays a code generation error with a
recommendation for changing the
Oversampling value. To clear
highlighting, click the
clearhighlighting script in the
MATLAB® Command Window.
Clock-Rate Pipelining and Hierarchy Flattening
You can use the clock-rate pipelining optimization with or without flattening the subsystem hierarchy. Flatten the subsystem hierarchy when you want to maximize opportunities for sharing resources in your design. To flatten the subsystem hierarchy, enable FlattenHierarchy on the top-level Subsystem. By default, all Subsystem blocks inside the top-level subsystem inherit this FlattenHierarchy setting. Hierarchy flattening brings several clock-rate regions to the same level in the hierarchy and combines them, which increases opportunities for clock-rate pipelining. However, it breaks the modularity of your design and affects the readability of the generated HDL code. See also Hierarchy Flattening.
To apply clock-rate pipelining without flattening the hierarchy, on the top-level subsystem in your model, disable FlattenHierarchy. If your design uses fixed-point data types, enable some optimizations on the underlying subsystems. In this case, the code generator introduces clock-rate pipelines in your design while preserving the subsystem hierarchy, which:
Improves the modularity of your design and makes navigation through the generated model easier especially in large designs with complex hierarchies.
Improves readability of the generated HDL code by creating multiple Verilog or VHDL files for the various Subsystem blocks in your design.
Clock-Rate Pipelining for DUT Output Ports
To insert DUT output port pipeline registers at the clock rate instead of the data
rate, select the Allow clock-rate pipelining of DUT output
ports option or use the
ClockRatePipelineOutputPorts property. This option changes
the timing of your DUT interface because it changes the sample time of your DUT
output ports from a slow rate to the clock rate. To adjust for the difference in
timing, HDL Coder generates messages that provides the phase offset of each output port.
For example, this message means that the output data from
portname is valid after 31 clock cycles:
Phase of output port
The validation model adjusts for the timing difference by inserting a Rate Transition block at the DUT output and comparing the output of the Rate Transition with the original output. The RTL test bench logs the output data at the input of the Rate Transition and compares it with the DUT output in the RTL simulation.
Best Practices for Clock-Rate Pipelining
If your design uses a Rate Transition block, switch the Rate Transition block with a Downsample block that has nonzero Sample offset. Clock-rate pipelining optimizes the Downsample block by avoiding the additional latency that the Rate Transition block can introduce, which saves area and timing.
Design your DUT at one rate and specify the Oversampling factor. Avoid using Rate Transition, Upsample, Downsample, or other rate-changing blocks.
Specify Clock-Rate Pipelining
You can set clock-rate pipelining on a model or, for finer control, on subsystems within the top-level DUT subsystem. By default, clock-rate pipelining is enabled on the model. To disable clock-rate pipelining from the UI:
In the Apps tab, select HDL Coder. The HDL Code tab appears.
Click Settings. In the HDL Code Generation > Optimization > Pipelining tab, clear Clock-rate pipelining and click OK.
At the command line, use the
hdlset_param function to set the
ClockRatePipelining property to
You can use clock-rate pipelining for a subsystem within the top-level DUT
subsystem. To model a control path in your design at the data rate instead of the
clock rate, put the control path in a subsystem, and disable clock-rate pipelining
for that subsystem. To disable clock-rate pipelining for a subsystem within the
top-level DUT subsystem, set ClockRatePipelining to
off for that subsystem. See also Set Clock-Rate Pipelining For a Subsystem.
Limitations for Clock-Rate Pipelining
These blocks inhibit clock-rate pipelining, and therefore delimit clock-rate pipelining regions:
Discrete PID Controller
Dual Port RAM
Dual Rate Dual Port RAM
FFT HDL Optimized
HDL Minimum Resource FFT
HDL Streaming FFT
MATLAB System, if it uses persistent variables
Simple Dual Port RAM
Single Port RAM
FlattenHierarchyis not enabled
The code generator does not support clock-rate pipelining for:
Black box subsystem or black box model reference blocks.
Subsystems that contain blocks not supported for clock-rate pipelining.
Altera DSP Builder subsystems.
Xilinx System Generator subsystems
Communications Toolbox™ blocks.
DSP System Toolbox™ blocks, except for Delay and Discrete FIR Filter.
The code generator does not support applying both the streaming and sharing optimizations on the same resource when you use the clock-rate pipelining optimization. Either disable clock-rate pipelining or use either the streaming optimization or the sharing optimization on the same resource when clock-rate pipelining is enabled.