Workflow Advisor

R2026b

Generate synthesizable HLS code and test benches from MATLAB code

Since R2022a

Description

Use the Workflow Advisor to convert MATLAB^® functions into High-Level Synthesis (HLS) code for FPGA and ASIC implementation.

The tool guides you through a step-by-step process to prepare, validate, and generate either HLS (SystemC™/SynthesizableC++) or HDL (VHDL^® or Verilog^®) code. You can use this tool to transition from MATLAB algorithm design to deployable hardware code. For more information on the MATLAB HDL Workflow Advisor, see Workflow Advisor.

With the Workflow Advisor, you can:

• Create a project or open an existing HDL Coder™ project.

• Perform fixed-point conversion.

• Generate synthesizable HLS code and corresponding test benches.

• Verify the numerical behavior of generated HLS code with an HLS test bench.

• Generate a customized IP core.

• Customize target and synthesis tool settings.

• Integrate with third-party FPGA tools for synthesis and implementation.

• Package and deploy your design to supported hardware platforms.

• Generate a programming file and download it to the target device.

Note

Workflow Advisor is not available in MATLAB Online™.

Open the Workflow Advisor

1. Type hdlcoder in the MATLAB Command Window.

   Alternatively, in the MATLAB Toolstrip, on the Apps tab, select HDL Coder.

2. In the Create HDL Coder Project dialog box, specify a project Name and Folder, then click OK to open the HDL Workflow Advisor.

3. In the HDL Workflow Advisor task, select the Code Generation Workflow.

4. In the Define Input Types task, add the design and test bench files:

   • For MATLAB Function, click Browse and select the MATLAB design file.

   • For MATLAB Test Bench, click the + button and select the MATLAB test bench file.

   • Click Run. The HDL Workflow Advisor runs the test bench to infer the input data types of the MATLAB design.

Note

Sometimes HDL Coder cannot determine whether the entry-point functions in your project are suitable for HDL code generation. The most likely reason is that HDL Coder is unable to find the entry-point files. Verify that your current working folder is set to the folder that contains your entry-point files. If it is not, either make this folder your current working folder or add the folder containing these files to the MATLAB path.

Examples

• Get Started with MATLAB to High-Level Synthesis Workflow Using HDL Coder App
• Get Started with HLS IP Core Generation Workflow

Parameters

HDL Workflow Advisor

Code Generation Workflow — Type of code to generate from MATLAB code

MATLAB to HDL (default) | MATLAB to HLS

Specify the type of code to generate from your MATLAB code:

• MATLAB to HDL — Generate HDL code in VHDL or Verilog.

• MATLAB to HLS — Generate HLS code in SystemC or SynthesizableC++.

Fixed-point conversion — Whether to convert floating-point data to fixed-point data

Convert to fixed-point at build time (default) | Keep original types

Specify whether to convert the floating-point data in your design:

• Convert to fixed-point at build time — Use the Fixed-Point Conversion tool to convert floating-point types to fixed-point during code generation.

• Keep original types — Retain the data types in the original MATLAB algorithm.

Build folder — Folder for files generated during the build process

Project folder (default) | Specified folder

Choose where to store generated build files:

• Project folder — Store build files in the project folder.

• Specified folder — Choose a custom location.

Build folder name — Name of build folder

no default

Enter a folder name in which to store the build files, or click Browse to select an existing folder.

Dependencies

To enable this parameter, set Build folder to Specified folder.

Define Input Types

MATLAB Function — Top-level MATLAB function

file name of MATLAB function

Specify the entry-point MATLAB function for code generation. Click Browse to select the design function.

MATLAB Test Bench — Test script that calls the MATLAB function

file name of test bench

Specify the test script or function that calls the MATLAB function for validation.

Use the Add a file button to add a new test bench and the Remove selected file button to remove the selected test bench.

Fixed-Point Conversion

Fixed-Point Conversion — Fixed-Point Conversion tool

Use the Fixed-Point Conversion tool to convert the floating-point data types in your DUT to fixed-point. For more information on how to use the Fixed-Point Conversion tool, see Automated Fixed-Point Conversion.

Dependencies

To enable this task, set Fixed-Point Conversion to Convert to fixed-point at build time.

Select Code Generation Target

Workflow — HLS code generation workflow

Generic ASIC/FPGA (default) | IP Core Generation

The HDL Workflow Advisor makes different options and downstream tasks available based on the workflow you select.

• Generic ASIC/FPGA — Generate SystemC/Synthesizable C++ code suitable for High-Level Synthesis using HLS tools.

• IP Core Generation — Generate a custom IP core and integrate it with embedded software in an embedded system integration project.

Platform — Target hardware platform for IP core generation

none (default) | Generic Xilinx Platform | Get more

Choose the hardware platform for which to generate the custom IP core. Your list of options might differ based on the products and support packages you have installed.

• Generic Xilinx Platform — Generates an IP core for integration with Xilinx FPGA hardware.

• Get more — Install an available HDL Coder support package if your hardware platform is not listed.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

Synthesis tool — Tool to synthesize generated HLS code

No synthesis tool specified (default) | Cadence Stratus HLS | Xilinx Vitis HLS | Xilinx Vivado

Choose the synthesis tool that matches your target hardware and development environment. You do not need to specify a synthesis tool if you want to generate generic HLS code. When you set Workflow to IP Core Generation, the setting you choose for Platform determines the settings that appear in this parameter.

• No synthesis tool specified — Use when you do not need to target a specific hardware device.

• Cadence Stratus HLS — Targets supported hardware using the Cadence^® Genus synthesis tool.

• Xilinx Vitis HLS — Targets AMD^® hardware. Requires specification of the Chip family and Device parameters.

• Xilinx Vivado — Targets AMD hardware using the Vivado^® tool. Xilinx Vivado is available only for IP Core generation. Requires specification of the Chip family, Device, Package, and Speed parameters.

If no synthesis tool appears in the list, ensure the tool is installed and its path is set up correctly. Then click Refresh list in the HDL Workflow Advisor.

Chip family — Chip family to target for synthesis

list of supported chip families

Choose your target device chip family to use for the synthesis tool. The options for this parameter depend on the setting of the Synthesis tool parameter.

Dependencies

To enable this parameter, set Synthesis tool to a setting other than No synthesis tool specified.

Device — Device to target for synthesis

list of supported devices

Choose the device to target for synthesis. This specification determines the specific hardware configuration that the synthesis tool uses during synthesis and implementation.

Dependencies

To enable this parameter, set Synthesis tool to a setting other than No synthesis tool specified.

Package — Physical packaging type of target device for synthesis

list of supported packages

Choose the target device package to use for synthesis. This specification determines the physical form factor and pin configuration that the synthesis tool uses during synthesis and implementation.

Dependencies

To enable this parameter, set Synthesis tool, Chip family, and Device to a synthesis tool, chip family, and device that supports different physical package types for synthesis.

Speed — Speed grade of target device for synthesis

list of supported speed values

Choose the speed grade of the target device to use for synthesis. This specification determines the timing characteristics that the synthesis tool uses during synthesis and implementation.

Dependencies

To enable this parameter, set Synthesis tool, Chip family, and Device to a synthesis tool, chip family, and device that supports different speed grades for synthesis.

Target frequency (MHz) — Clock frequency for generated HDL design

0 (default) | positive scalar

Specify the target clock frequency, in MHz, for the generated HDL design. Use this value to configure the clock module and timing constraints during synthesis and implementation.

Reference design — Predefined embedded system integration project for IP core insertion

list of available reference designs

Select the predefined embedded system integration project into which HDL Coder inserts your generated IP core. The reference design defines the hardware and software environment for integrating and testing the IP core.

To create a reference design, see Register a Custom Reference Design.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

IP core name — Name of generated IP core

name of generated IP core

Enter a name for the generated IP core. The app uses this field to name the IP core in the generated files. For example, if you enter myFilter, the tool generates an IP core named myFilter_ip.

If this field is empty, the tool uses the name of the top-level MATLAB function as the base name for the IP core.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

IP core version — Version identifier for generated IP core

version identifier

Enter a version number or label for the generated IP core. The tool includes this value in the IP core metadata. Use this value to track changes across iterations.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

IP core vendor name — IP core vendor name

vendor name

Enter the IP core vendor name. The vendor name must not start with a numeric character (for example, 23network is invalid), and must not contain whitespace characters (for example, net work is invalid). The vendor name does not need to include a domain suffix such as .com or .net.

You can specify the vendor name only when you set the Target workflow to IP Core Generation and the Synthesis tool to Xilinx Vivado.

Processor/FPGA synchronization — Synchronization behavior between processor and FPGA

Free running (default) | Coprocessing-blocking

Select how the processor and FPGA operate relative to each other during execution:

• Free running — The processor and FPGA run independently without automatic synchronization.

• Coprocessing-blocking — HDL Coder generates synchronization logic so the processor waits for the FPGA to complete execution before continuing. Use this option when the FPGA execution time is short relative to the processor sample time.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

Note

To enable the Set Target Interface tab, in Select Code Generation Target, set Workflow to IP Core Generation.

Select Code Generation Target > Set Target Interface

Set Target Interface — MATLAB design

Select the Set Target Interface task to see the fixed-point representation of the MATLAB design. The app generates this code using Fixed-Point Designer™.

Ports — Port information

no default

The Ports table displays the properties of the input and output functions. Use this table to map these functions to I/O resources on the target device. The table contains these sections:

• Inport – Lists input functions to the design

• Outport – Lists output functions from the design

The app displays the function names and their data types in these sections. Use the Target Platform Interfaces and Bit Range / Address / FPGA Pin columns to map each function to a hardware interface and physical or logical resource on the target platform.

Column Name	Description
Port Name	The name of the function in the MATLAB design. This field is read-only.
Data Type	The data type assigned to the function. This field is read-only.
Target Platform Interfaces	Specify the interface type on the target hardware platform. For example: AXI4-Lite AXI4 Master Read AXI4 Master Write External Port Available options depend on your Device selection.
Bit Range / Address / FPGA Pin	Specify the connection details for the selected interface type: If you set the Target Platform Interface to External Port, assign the physical I/O pins by entering a cell array of FPGA pin names. For example, {'A10','B10','C10'}. If you set the Target Platform Interface to AXI4-Lite, specify the memory-mapped address offset. For example, 0x00, 0x04. If you set the Target Platform Interface to AXI4-Master, it maps the input read and output write channels to Data port. For example, Data.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

Build Log — Display log of code generation process

no default

The Build Log tab displays the detailed messages and status updates generated during the code generation process.

Dependencies

To enable this parameter, set Workflow to IP Core Generation.

HLS Code Generation > Target

Language — HLS code generation language

SystemC (default) | SynthesizableC++

Specify the HLS language for the generated code. When Synthesis tool is set to:

• No synthesis tool specified – Target language is set to SystemC.

• Cadence Stratus HLS – Target language is set to SystemC.

• Xilinx Vitis HLS – Target language is set to SynthesizableC++.

• Xilinx Vivado – Target language is set to SynthesizableC++.

Dependencies

Synthesis tool Xilinx Vivado is only available when the Workflow is IP Core Generation.

Check HDL conformance — Check MATLAB design for HLS code generation compatibility

off (default) | on

Select this parameter to analyze your MATLAB design and ensure it is compatible for HLS code generation.

Generate report — Generate code generation report

on (default) | off

Select this parameter to generate an HTML report that provides traceability information and details about the generated HDL code.

Enable traceability — Generate traceability report

on (default) | off

Select this parameter to generate an HTML report that provides traceability information.

HLS Code Generation > Coding Style

Preserve MATLAB code comments — Retain MATLAB comments in generated HLS code

on (default) | off

Select this parameter to preserve comments from the original MATLAB code in the generated HLS code.

Include MATLAB source code as comments — Insert MATLAB source code as comments in generated HLS code

off (default) | on

Select this parameter to include the original MATLAB source code as comments in the generated HLS code.

Emit time/date stamp in the header — Include timestamp in generated HLS file headers

on (default) | off

Select this parameter to include the current time and date in the header comments of each generated HLS file. This can help track when the code was generated for versioning or audit purposes.

Comment in header — Custom comment to include in HLS and test bench file headers

string

Specify a comment to insert at the top of each generated HLS and test bench file. Use this to include author information, project details, or version notes.

Module name prefix — Prefix string for generated DUT module or entity name

string

Specify a prefix to prepend to the name of the generated DUT module in Verilog or SystemVerilog, or entity in VHDL. This helps customize naming to match project or organizational conventions.

Complex real part postfix — String to append to real part of complex signal names

_re (default) | string

Specify a string to append to the names of the real part of complex signals in the generated HLS code. This helps distinguish real and imaginary components when complex data types are split during code generation.

Complex imaginary part postfix — String to append to imaginary part of complex signal names

_im (default) | string

Specify a string to append to the names of the imaginary part of complex signals in the generated HLS code. This helps distinguish real and imaginary components when complex data types are split during code generation.

Reserved word postfix — String to resolve HLS reserved word conflicts

_rsvd (default) | string

Specify a string to append to names of entities, signals, constants, or other MATLAB code elements that conflict with reserved words in the target HLS language. HDL Coder uses this postfix to ensure the generation of valid and synthesizable HLS code.

Create Regions automatically in the generated code — Create regions in the generated HLS code

off (default) | on

Select this parameter to create regions in the generated HLS code. Use these regions to perform design space exploration using the HLS tools. The code generator stores the generated region labels in the ml.tcl file when you set the synthesis tool to Cadence Stratus HLS.

HLS Code Generation > Optimizations

Map persistent array variables to RAMs — Whether to map all persistent array variables to RAM

on (default) | off

Select this parameter to map all persistent array variables to RAM to reduce area.

RAM mapping threshold — Minimum RAM size to map all persistent array variables and delays to RAM

256 (default)

Specify the minimum RAM size to begin mapping all persistent array variables and delays to block RAM. You can specify the minimum RAM mapping threshold either by using a single integer or by specifying the thresholds for the data:

• To map persistent array variables to RAM when the RAM size is greater than this threshold, in bits, use a single integer. To calculate the total RAM size for persistent arrays, use this formula:

  RAMSize =  Array size * Word length * Complexity

  Complexity is 2 for a complex data type or 1 for a real data type. To calculate the total RAM size for delays, use this formula:

  RAMSize = Delay length * Word length * Vector length * Complexity

• To specify one threshold for the array size (for persistent arrays) or delay length (for delays), and one threshold for the word length or bit width of the data type, enter the thresholds in the format MxN.

  For example, to specify a delay length of 500 cycles and word length of 50 bits, enter 500x50.

• Using a string of format MxN that specifies two thresholds to define the shape of the data to map to RAM, one for array size (for persistent arrays) or delay length (for delays) and one for word length or bit width of the data type.

Initialize block RAM — Whether to initialize all RAM elements to zero for simulation

on (default) | off

Select this parameter to initialize all block RAM elements to zero for simulation.

Saturate on integer overflow — Choose to generate saturation logic in HLS code for integer data types

on (default) | off

Specify whether HDL Coder generates HLS code to handle integer overflow. Overflow saturates to either the minimum or maximum value the data type can represent.

This parameter only applies to MATLAB built-in integer data types. It does not apply to double, single, or fixed-point data types.

HLS Code Generation > Advanced

Generate instantiable code for functions — Choose to generate instantiable HLS code modules

off (default) | on

Specify whether to generate instantiable HLS code modules from functions.

Array Layout — Choose the array layout for HLS code generation

Column Major (default) | Row Major

Specify the array layout for HLS code generation.

Code Replacement Library — Code replacement library name

None (default) | library name

Code replacement library name, specified as a character vector or string scalar. Use code replacement libraries to replace MATLAB functions and operators with custom C/C++ implementations in the generated HLS code.

Code Replacement Report — Generate a code replacement report

off (default) | on

Select this parameter to generate a report that shows which functions and operators in the generated code were replaced by the code replacement library.

Additional Tcl File — Specify additional Tcl file for synthesis

none (default)

Specify an additional Tcl file to include during synthesis. Use the browse button to navigate to and select the Tcl file. The Tcl file can contain additional synthesis constraints or commands for the synthesis tool.

HLS Code Generation > Code

Code — Display MATLAB DUT

Display the MATLAB DUT in the MATLAB Workflow Advisor.

Note

To enable the Verification tab, in Select Code Generation Target, set Workflow to High Level Synthesis.

Verify with HLS Test Bench > Output Settings

Generate test bench — Generate HLS test bench code from MATLAB test bench

on (default) | off

Specify whether to generate HLS test bench code from MATLAB test bench stimulus.

Simulate generated test bench — Simulate HLS DUT using generated HLS test bench and HDL simulator

off (default) | on

Specify whether to simulate the HLS DUT with the generated HLS test bench code with an HDL simulator.

Dependencies

To enable this parameter, Simulation tool must be set to a value other than No simulation tool available on system path.

Simulation tool — Simulation tool to simulate generated HLS test bench

MATLAB Host (default) | Xcelium Simulator | Xilinx Vitis HLS | No simulation tool available on system path

Simulation tool to simulate the generated HLS test bench. After you set up your simulation tool, click Refresh list to make the tool available in the HDL Workflow Advisor.

Dependencies

Selecting Simulate generated test bench enables this option. The value of the Simulation tool depends on your selection of the Synthesis tool.

Verify with HLS Test Bench > Test Bench Options

Floating point tolerance check — Method to use for floating-point tolerance comparison

Relative Error (default) | ULP Error

Specify the method to use for the floating-point tolerance check of the generated code with respect to the floating-point DUT.

Setting	Result
Relative Error	HDL Coder checks for the floating-point tolerance of the native floating-point library or the floating-point target library that the DUT mapped to based on the relative error.
ULP Error	HDL Coder checks for the floating-point tolerance of the native floating-point library or the floating-point target library that the DUT mapped to based on the ULP error.

Tolerance Value — Floating-point tolerance to use for Floating point tolerance check strategy

1e-07 (default) | 0

Specify the tolerance value to use for the Floating point tolerance check method. The default value for Tolerance Value changes depending on the value of the Floating point tolerance check parameter.

Floating point tolerance check Value	Result
Relative Error	By default, Tolerance Value is set to 1e-07. Set Tolerance Value less than or equal to 1e-07. Specify the tolerance value as a double data type.
ULP Error	By default, Tolerance Value is set to 0. Set Tolerance Value greater than or equal to 0. Specify the tolerance value as an integer data type.

Note

To enable the Synthesis and Analysis tab, in Select Code Generation Target, set Workflow to High Level Synthesis and select the Synthesis tool.

Synthesis and Analysis > Run Synthesis

Skip this Step — Whether to skip Run Synthesis step

off (default) | on

Select this parameter to skip the Run Synthesis step.

Embedded System Integration > Create Project

Embedded system tool — Display third-party embedded system tool for IP core project creation

Displays the third-party embedded system tool to use to create the IP core project.

HDL Coder determines the value for the Embedded system tool parameter based on the value of the Synthesis tool parameter.

Project folder — Display location of generated IP core project files

codegen/pa_prj (default)

Displays the name of the folder where the third-party synthesis tool generates and saves project files.

Embedded System Integration > Generate Software Interface

Skip this Step — Whether to skip Generate Software Interface step

on (default) | off

Select this parameter to skip the Generate Software Interface step.

Embedded System Integration > Build Embedded System

Run build process externally — Whether to generate bitstream externally

off (default) | on

Select this parameter to generate the bitstream in a separate processes in parallel with your current MATLAB instance. If this option is disabled, you cannot use MATLAB until the build is finished.

Embedded System Integration > Program Target Device

Skip this Step — Whether to skip Program Target Device step

off (default) | on

Select this parameter to skip the Program Target Device step.

Programming method — Method to program the target device

Download | JTAG | Custom

Specify the programming method for the target device.

• Download — Copies the generated FPGA bitstream, Linux devicetree, and system initialization scripts to the SD card on the target board, and keeps the bitstream on the SD card persistently. This is the default method for SoC hardware platforms. To use this method, you do not require an Embedded Coder license. HDL Coder uses an SSH object to copy the bitstream to the SD card and reprogram the board. You can create the SSH object by specifying the IP Address, SSH Username, and SSH Password.

  Use the Download method because it programs the FPGA bitstream and loads the corresponding Linux devicetree before booting the Linux system. This method is more robust and does not result in a kernel panic or kernel hang on boot up. During the Linux reboot, the FPGA bitstream is reprogrammed from the SD card automatically.

• JTAG — Uses a JTAG cable to program the target device. Use this method to program SoC platforms and standalone FPGA boards. JTAG is the default method for standalone FPGA boards that do not have an embedded ARM processor.

  For SoC devices, use the Download method instead. The JTAG mode programs the onboard FPGA directly without involving the ARM processor and does not update the Linux devicetree. This can crash the Linux system or result in a kernel panic when the bitstream does not match the devicetree.

• Custom — Uses a custom programming method that you define in your own custom reference design. Use the CallbackCustomProgrammingMethod property of the hdlcoder.ReferenceDesign class to register a function handle for the callback function that runs when you execute the Program Target Device task. To define your callback function, create a file that defines a MATLAB function and add the file to your MATLAB path. For more information, see CallbackCustomProgrammingMethod.

IP Address — IP address of the target board

string

Specify the IP address of the target board. HDL Coder uses this IP address to create an SSH connection to the board for programming.

Dependencies

To enable this parameter, set Programming method to Download.

SSH Username — SSH username for the target board

string

Specify the SSH username for connecting to the target board. HDL Coder uses this username to create an SSH connection to the board for programming.

Dependencies

To enable this parameter, set Programming method to Download.

SSH Password — SSH password for the target board

string

Specify the SSH password for connecting to the target board. HDL Coder uses this password to create an SSH connection to the board for programming.

Dependencies

To enable this parameter, set Programming method to Download.

Version History

Introduced in R2022a

R2026b: Specify code replacement libraries, additional Tcl files, and target device programming settings

In the HLS Code Generation > Advanced tab, you can now specify a Code Replacement Library to replace MATLAB functions and operators with custom C/C++ implementations in the generated HLS code. To verify which functions and operators the library replaced, generate a Code Replacement Report.

Use the Additional Tcl File option to include synthesis constraints or commands for the synthesis tool.

In the Embedded System Integration > Program Target Device tab, you can now select a Programming method (Download, JTAG, or Custom) and configure the IP Address, SSH Username, and SSH Password to connect to the target board for programming.