# Modulo by Constant HDL Optimized

Perform mod operation with a constant denominator and generate optimized HDL code

**Library:**Fixed-Point Designer HDL Support / Math Operations

## Description

The Modulo by Constant HDL Optimized block performs the modulo operation (remainder after division) with a constant denominator using an HDL-optimized architecture with cycle-true latency.

The Modulo by Constant block uses an algorithm that is functionally similar to a Barrett Reduction. The division operation is computed via a multiplication by inverse, which generally results in better performance on embedded systems.

## Ports

### Input

### Output

## Parameters

## Model Examples

## Algorithms

The Modulo by Constant HDL Optimized block performs the modulo operation (remainder after division) with a constant denominator using an HDL-optimized architecture with cycle-true latency.

The modulo operation,

$$Y=X\mathrm{mod}D=X-\lfloor \frac{X}{D}\rfloor \times D$$

is an important building block for many mathematical algorithms. However, this formula for *X* mod *D* is computationally inefficient for fixed-point and integer inputs. Many
embedded processors lack instructions for integer division. Those that do have them require
many clock cycles to compute the answer. Division is also inefficient in
commercially-available FPGAs, whose arithmetic circuits are designed for efficient
multiplication, addition, and subtraction. Finally, for fixed-point modulo operations, it is
difficult to optimize the word length of internal data types used for the calculation because
the division operation is unbounded, even for small-wordlength inputs.

The denominator in the modulo problem is a compile-time constant, so the block can compute the floored division by using a multiplication followed by a cast. Rewriting the division operation as

$$\frac{X}{D}=X\times \frac{1}{D}$$

shows this. The constant is calculated to the precision necessary to maintain both accuracy and computational efficiency. The cast that follows discards any fractional bits, which is an efficient operation on both microprocessors and FPGAs.

The Modulo by Constant block uses an algorithm that is functionally similar to a Barrett Reduction. The division operation is computed via a multiplication by inverse, which generally results in better performance on embedded systems.

## Extended Capabilities

## See Also

**Introduced in R2021a**