Today’s storage devices, including solid state drives (SSDs) and hard disk drives (HDDs), require advanced signal processing subsystems for high-speed data encryption and error correction. In many organizations, engineers develop the initial algorithms for these subsystems in C or C++. The algorithms are then used as reference models for writing and verifying HDL code for FPGA or ASIC implementation. Translating the reference C algorithms to HDL is both time-consuming and error-prone, as engineers have to map the sequential behavior of C to the parallel behavior of hardware. This process makes design iterations very difficult.
Engineers at Siglead Inc. use Model-Based Design with MATLAB® and Simulink® to bridge the gap between algorithm development and HDL implementation. “Moving from a reference model designed by an algorithm engineer to the HDL or RTL implementation developed by hardware engineers can be difficult because the engineers come from such different backgrounds,” says Atsushi Esumi, president and CEO at Siglead. “With MATLAB and Simulink, our algorithm engineers can generate HDL on their own. This accelerates development and enables our hardware engineers to concentrate on other critical design tasks, such as speed and size optimization.”