Chapter 4
FPGA-Based Debug and Verification
Debug and Test Designs on FPGA Development Boards
The ultimate test of an algorithm is whether it performs as specified in hardware. With MATLAB and Simulink, you have a variety of methods for testing algorithm implementation on FPGA development boards.
- You can program the design-under-test (DUT) into a development board and run tests with your MATLAB or Simulink session acting as its testbench, letting you subject the hardware prototype to a range of stimuli while visualizing results interactively.
- To debug and test your DUT at speed, you can insert probes on internal signals of interest, capture signals during tests on hardware prototypes, and then retrieve signals for viewing and analysis in MATLAB.
- You can interactively control IP cores programmed into your FPGA board from MATLAB through read/write access to their AXI4-accessible registers.
These methods provide different levels of interactivity and visibility to meet a variety of your test and verification needs.
Use FPGA-in-the-Loop for Hardware-Based Verification
Using FPGA-in-the-loop (FIL) testing, you can perform back-to-back testing of your hardware implementation with the golden reference model in MATLAB or Simulink.
With FIL, you program the DUT into a development board from AMD, Intel, or Microchip and apply the testbench just as you would in HDL cosimulation. The MATLAB or Simulink testbench executes on a host computer, passing signals to and from the development board. FIL can provide hardware acceleration of testing compared with HDL cosimulation.
The tool automates all steps to set up and perform FIL testing, including compiling the DUT using AMD Vivado, Intel Quartus®, or Microchip Libero® SoC; programming the development board; and setting up communication via JTAG, Ethernet, or PCI-Express.
More than 50 boards from AMD, Intel, Microchip, and others are supported, and you can extend FIL to work with custom boards.
Capture Signals with FPGA Data Capture
FPGA-in-the-loop testing has two conditions that affect where it can be used most effectively:
- Communication between the host computer and the development board means the DUT must be clocked at reduced rates.
- All inputs to the DUT must originate in MATLAB or Simulink, so inputs cannot come from other development board inputs.
When you want to run tests at speed and not be limited to inputs from the host computer, the FPGA Data Capture too can provide a better option.
With FPGA Data Capture, you can generate IP cores that probe specific internal signals of your FPGA implementation and save them to local memory. The signals can then be brought into MATLAB or Simulink for viewing and analysis.
If you are using HDL Coder to generate RTL, you can add test points in your Simulink model to specify which signals of your model should be retrieved, no matter where they are in the model’s hierarchy.
With FPGA Data Capture, you can define trigger conditions and specify the number of data samples retained so you can debug the hardware implementation. Signals can be viewed as in the Logic Analyzer window, which provides cursors and other tools for measuring and evaluating signals.
Read from and Write to Registers and DDR Memory
There are many times when you need to have read/write access to AXI4-accessible registers or memory on FPGA development boards. One example would be when you are testing a new IP core that’s been implemented in programmable logic.
In such cases, engineers often need to write C code for an Arm® processor core solely for the purposes of testing the core by accessing AXI4 registers. Such C code enables testing but is ultimately throwaway code.
The MATLAB AXI Master feature enables you to read from or write to registers or DDR memories from your MATLAB session, giving you the ability to extend MATLAB analysis scripts for testing and avoid the need to write embedded C code simply for testing.
