Channelizers are playing an increasing role as a way to manage the ever-widening bandwidth of digitized signals in radar and communications systems. Given their high frequency operation, inherent parallelism, and high-speed I/O, FPGAs provide an ideal platform for implementing channelizers.

In this webinar, engineers from MathWorks and Altera demonstrate how to use MathWorks products to design and implement channelizers on Stratix V FPGAs from Intel. You will learn how to construct testbenches and generate stimulus using MATLAB code. We use an example based on a reference design to show how a Simulink model of the channelizer can be targeted to a Stratix V using DSP Builder for Intel FPGAs.

We cover the use of HDL cosimulation and FPGA-in-the-loop with the DSP Development Kit, Stratix V Edition from Intel to verify that the original Simulink models have been correctly implemented.

Who should attend:

• Radar algorithm developers
• Communications designers
• Hardware designers
• Verification engineers

About the Presenters:

Robert Anderson is a Principal Application Engineer for signal processing and communications at MathWorks, with a focus on FPGA implementation.  Robert has over 25 years of experience in hardware design and implementation. He earned his MS. in electrical and computer engineering from Northwestern University.

Ronak Shah is the Manager of Systems Engineering for Altera Corporation, where he and his team develop complex digital signal processing algorithms for implementation on Intel (formerly Altera) FPGAs. Ronak earned a BSEE at Cal Poly in San Luis Obispo and an MSEE at UC Santa Barbara.