Answered
IP core generation for built-in Simulink model
Unfortunately we do not have your contact in our tech support database. Can you reach out to our support team via email to suppo...

2 years ago | 0

Answered
is there a way to define 'fixdt' in a Matlab script and use this variable in a Simulink User-Defined Function?
Can you share a bit more details of this usecase? A sample model would be helpful. Are you using this in the context of a MATL...

2 years ago | 0

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Answered
Trouble with Vitis Model Composer 2023.2! MATLAB R2021b crashes when I want to open the Model Composer Hub component.
This might be related to a known MATLAB issue: https://www.mathworks.com/matlabcentral/answers/364551-why-is-matlab-unable-to...

2 years ago | 1

Answered
IP core generation for built-in Simulink model
Please share your model if possible. I am attaching few sample design patterns that show how to build HDL Coder compliant desi...

2 years ago | 0

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what is the difference between FPGA Turnkey and IP Core Generation?
Targeting FPGA & SoC Hardware with HDL Coder Workflow Design a system that you can deploy on hardware or a combination of h...

2 years ago | 1

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Force MATLAB code to run on hardware
Please share your code / model that you want to generate HDL from. if you are taking the ML/DL route, please consider https://w...

2 years ago | 0

Answered
How to create a simulink model for testbench
You need a testbench and HDL DUT subsystem to generate a valid RTL design and testbench from a Simulink model >> makehdl('l...

2 years ago | 0

Answered
Error while generating HDL code from Simulink for Canny Edge Detection
For pure pixel in and pixel out based streaming interface DUT, the blocks such as frame to pixel and pixel to frame should be ou...

2 years ago | 0

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Answered
HDL Coder For Each Subsystem Assertion failed: B:\matlab\src\cgir_hdl\pir_tags\ForEachDataTag.hpp:178:nativeVObj.get()
The error message is not expected. Can you share your model? Either HDL Coder needs to generate code from the model or generate ...

2 years ago | 0

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Answered
How to get the stored integer representation of a single-precision floating point in simulink (HDL Coder)?
https://www.mathworks.com/help/hdlcoder/ref/floattypecast.html Float Typecast Typecast a floating-point type to an unsigned in...

2 years ago | 1

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Answered
wait statement without UNTIL clause not supported for synthesis Error when using HDL coder
Please reach out to tech support if this issue is still reproducible. % Copy the AES demo files to a temporary folder mlhdlc_d...

2 years ago | 0

Answered
Matlab code generation and support for Xilinx Cora Z7-07S
HDL Coder doesn't have explicit support for this board, but the closest board that we support looks to be the ZedBoard or ZC702....

2 years ago | 0

Answered
SystemC code generation directly from SIMULINK model
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workfl...

2 years ago | 0

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Assertion Error in HDL Coder
This is not an expected error from the product. Can you please provide the reproduction steps with support team? We will try to ...

2 years ago | 0

Answered
Multiple IOSTANDARDs for a single HDL coder interface
https://www.mathworks.com/help/hdlcoder/ref/hdlcoder.board.addexternaliointerface.html addExternalIOInterface('InterfaceID',int...

2 years ago | 1

Answered
Error running simulink with QuestaSim. Failed to connect to server. Make sure loaded HDL simulator library is using shared memory.
It looks like you are generating cosimulation model from HDL Coder. The issues seems related to either installation of the HDL...

2 years ago | 0

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HDL FIFO Reset Problem
Would you be able to share your sample model? You can prune it to just show HDL FIFO block. Found a relevant report here. Need ...

2 years ago | 0

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Error while using vector real gateway in
https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html This issue needs to be posted to AMD tech suppor...

2 years ago | 0

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Delay balancing error using R2023b, but have not experienced this in R2017b
The model fails code generation due to pipeline requests at the faster rate that need to be balanced. Need to review generated...

2 years ago | 0

Answered
How do i define an array as a HDL input?
It would be helpful to share your model. HDL Coder supports vector inputs at the DUT interface. Attached is an example of 40poi...

2 years ago | 2

Answered
add_block from other toolboxs
Run this command to see the supported block list. >> hdllib('html') ### HDL supported block list hdlblklist.html ### HDL impl...

2 years ago | 0

Answered
Scalarize Vector Ports option get the HDL code running time is infinite
You have unsynthesizable IO in your model. Please consider IO optimization to convert the frame model to sample model manually o...

2 years ago | 0

Answered
From Simulink to Vivado
Closing the thread. This error is not reproducible since 2019a release. Please reach out to tech support if you see the issue...

2 years ago | 0

Answered
How can i generate a triangular wave form using HDL supported blocks
See the attached sample model (with updown carrier type) you can generate triangular wave. Some examples you may also find ...

2 years ago | 0

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Answered
SIMULINK - HDL code generation with floating point & matlab function block
This restriction is relaxed since R2019b. Simulink Blocks Supported by Using Native Floating Point https://www.mathworks.com/...

2 years ago | 0

Answered
Icc64.exe has stopped working
Please check the supported compilers here https://www.mathworks.com/support/requirements/supported-compilers.html Please note a...

2 years ago | 0

Answered
Get inverse of scalar in hdl code generation
There are multiple ways to generate HDL from HDL with reciprocal and divide operators. If the scalar variable you are computin...

2 years ago | 0

Answered
IP core generation fails with vivado error
Closing this unanswered thread. This issue is resolved starting R2016a release. Please reach out to tech support if you see th...

2 years ago | 0

| accepted

Answered
Generate a PWM in FPGA using a customised carrier.
There are several pulse generator blocks in the Simulink library that are on the HDL Coder roadmap for automatic code generation...

2 years ago | 0

Answered
Dynamic LUT in HDL coder
LUT with BP data as an input is a work in progress feature in HDL Coder. Reach out to tech support for your requirements. Unt...

2 years ago | 0

| accepted