Answered
How to optimize multiplications with hdl coder
ConstMultiplierOptimization The ConstMultiplierOptimization implementation parameter lets you specify use of canonical signed d...

5 years ago | 1

Answered
What is the good manner of generating the HDL Code of a mixed Simscape/Simulink model ?
Simscape Hardware-in-the-Loop Workflow Automatic replacement of Simscape subsystem with state-space implementation In R2020b, ...

5 years ago | 1

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Answered
Internal Error in generation of HDL IP core for a Xilinx platform
Can you explain why you would need to force the subsystem to be atomic for Zynq targeting? I totally understand the additional ...

5 years ago | 0

Answered
Internal Error in generation of HDL IP core for a Xilinx platform
Firstly, you need to fix algebraic loop option on the FPGA DUT by turning off this option as follows set_param('PID_example2...

5 years ago | 0

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How can i generate testbench data for fixed point range
Hi, for better guidance, can you share your sample model that you plan to take to HDL code generation? Thanks.

5 years ago | 0

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How to connect bus data type to external port interface?
Bus support for External Port is not yet supported in HDLCoder and is under active development and will be available in the near...

5 years ago | 0

Answered
Why it occur overflow??
The overflow behavior is based on what kinds of operations are happening on the variable. Is it in a feedback look like a for-lo...

5 years ago | 1

Answered
CWT Filter Bank Function
Generating code FPGA cannot support variable dimensions as HDLCoder needs to generate code for a chip with fixed size, type, dim...

5 years ago | 0

Answered
Is there a way to change the parameter in simulink??
Have you considered using to workspace and from workspace blocks and logging your time series data and reading it back in?

5 years ago | 0

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Answered
Is there a 'block' similar to MATLAB's 'persistent' in simulink??
I am not using any new Simulink features; so you can try to load the model in your version. Try this to load the model. >> s...

5 years ago | 1

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Is there a 'block' similar to MATLAB's 'persistent' in simulink??
Attached model shows how to model unit delay, integer delay, tapped delay in MALTAB and corresponding blocks/modeling patterns i...

5 years ago | 0

Answered
HDL Workflow Advisor error
Hi, This is an unexpected internal error. Can you share the model?

5 years ago | 0

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Answered
HDL Coder returns with error "Unrecognized fixed-point encoding"
can you reach out to support@mathworks.com to help debug this error further? thanks

5 years ago | 0

Answered
Codegen parfor + singleC
parfor support is an active area of development for -singleC feature; please feel free to reach out to us support@mathworks.co...

5 years ago | 0

Answered
Cell arrays are not supported when using the -singleC flag (Coder)
cell array support is an active area of development for -singleC feature; please feel free to reach out to us support@mathwork...

5 years ago | 0

Answered
Matlab Options for Programming Labview R-series FPGA card.
Please let us know if this tutorial is somethign that can be used in your case. MATLAB®, Simulink®, and LabVIEW FPGA: Importing...

5 years ago | 0

Answered
HDL Coder returns with error "Unrecognized fixed-point encoding"
Hi Tim, Based on the error message this does not seem to be coming during code generation process. Are you sure you able to com...

5 years ago | 0

Answered
HDL code generation from simulink and dumping process
The question is a bit vague; can you provide more specifcis on your workflow issues? HDLCoder should support cyclone V workflo...

5 years ago | 0

Answered
how to use exp funnction in hdl coder?
Hi, Can you add more details and share example files with projects and reproductions here so that we can give better guidance?...

5 years ago | 0

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Implementation Latency of Blackbox Subsystem when using oversampling
We are also able to generate code for the mockup model.

5 years ago | 0

Answered
Implementation Latency of Blackbox Subsystem when using oversampling
With HDLCoder we have done a very detailed Fied-Oriented Controller model on FPGA/SoC. See the attached document. Happy to...

5 years ago | 0

Answered
Matlab coder, fixed point conversion
Hi Jerome, Can you share a sample of MATLAB code with floating-point and expected integer type code from fixed-point converter?...

5 years ago | 0

Answered
Can't open HDL Workflow Advisor
Glad the solution helped. It is quite possible the device you are planning to use is not supported in 19a. You can check this...

5 years ago | 0

Answered
Can't open HDL Workflow Advisor
Please try this and if this does not help it is best to have a clean install. >>Advisor.Manager.refresh_customizations Or >>r...

5 years ago | 0

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Answered
Can't open HDL Workflow Advisor
May I know the version of MATLAB you are using? I wonder if this can occur due to faulty installation of MATLAB or any support ...

5 years ago | 0

Answered
How can I add input port in HDL workflow advisor after running simulink model?
At the boundary, you need to have scalar and small vector inputs; full frame input is not allowed. https://www.mathworks.com/h...

5 years ago | 0

Answered
Delay balancing unsuccessful because Signal rate of value inf found.
I still see "Inf" sample times in the model. Found the Model was feeding 'Inf' sample time into the DUT. This is not allo...

5 years ago | 0

Answered
Delay balancing unsuccessful because Signal rate of value inf found.
Your model is partially converted to fixed-point. Can you check for absence of floating-point if your intent is HDL code gener...

5 years ago | 2

Answered
hdl coder supported in Cyclone 10 LP from Intel.
HDLCoder generates code targetable for all Intel FPGA families including Cyclone 10. https://www.mathworks.com/products/hdl-co...

6 years ago | 0

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Answered
Evaluation of elaborate function error in HDL coder
This is an unexpected error from HDLCoder. Will it be possible to share the model? We can evaluate and provide the workaround. ...

6 years ago | 0