Answered
How can I convert from decimal to binary for HDL Coder?
Attaching the model in the example for convenience.

5 years ago | 0

Answered
Data type issue for LUT input
hdlcoderFocCurrentFixptHdl should generate HDL out of the box. >> makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control') ...

5 years ago | 0

Answered
hdlcoder std_logic_vector to stateflow type
Attached simple Stateflow chart will generate the code you are looking for.

5 years ago | 0

Answered
can we generate HDL code for matrix multiplication ?
hi satish, can you share more details?are both A and B inputs to the DUT or only one of them, what are the types, are you lookin...

5 years ago | 0

Answered
HDL-Coder AXI-Vector Strobe Register validation model
HDL Coder does not currently support adding additional logic to the validation model.

5 years ago | 1

Answered
HDL Coder: How to create a resettable delay that triggers on rising edge
Please find attached two variations of the model generating HDL code. Simulink “Counter Limited” block with dynamic upper limit...

5 years ago | 1

| accepted

Answered
Error with cosimulation on tunable parameters
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedvision/ug/fpga-targeting-workflow.html yes, You can target zed board u...

5 years ago | 0

Answered
About hdlsllib/HDL RAMs blocks
>> How can we load data to the RAM or ROM block in simulink?

5 years ago | 0

Answered
Error with cosimulation on tunable parameters
This is a limitation in the cosimulation test bench generation. Can you consider using stand-alone testbench with HDL Simulato...

5 years ago | 0

Answered
Delay Balancing Error (RTL Code/ IP Core generation)
https://www.mathworks.com/help/hdlcoder/ug/delay-balancing.html You need to work towards not introduce delays in feedback loops...

5 years ago | 0

Answered
HDL Coder Error: BITAND/BITOR/BITXOR must have matching operand types
HDL Coder team believes this issue has been resolved in the latest releases. Can you share a sample model? We can double check a...

5 years ago | 1

| accepted

Answered
Getting Started with Targeting Xilinx Zynq Platform
(follow up from my team) Hi Kiran, I think I might know the issue. In one of the images, I can see the Tool Version text box...

5 years ago | 0

Answered
Slow simulation time ins simulink.
“How do I model the clock signal?” – is a question frequently asked by hardware engineers who are new to using Simulink and HDL ...

5 years ago | 0

| accepted

Answered
Field oriented control speed controller hdl conversion
Field-Oriented Control of a Permanent Magnet Synchronous Machine In this example you will review a Field-Oriented Control (FOC)...

5 years ago | 0

| accepted

Answered
Getting Started with Targeting Xilinx Zynq Platform
The error essage seems to indicate this is an issue with Xilinx Vivado installation? Task "Vivado IP Packager" unsuccessful. ...

5 years ago | 0

Answered
HDL Workflow Advisor Error from inf SampleTime
This issue is actively resolved. Please reach out to support@mathworks.com for additional support on this issue. Thanks

5 years ago | 0

Answered
HDL coder and Embedded coder interaction
If your target hardware requires you to generate C and HDL code it is better to split your design into two subsystems or two mod...

5 years ago | 0

| accepted

Answered
Sampling rate conversion issues in HDL coder
See attached QPSK Tx, Rx example that works with HDL Coder. You can read through instructions in QPSKTxRxHDLExample.m on how to...

5 years ago | 0

Answered
instrumented MEX function...and HDL code...
The original question is related to floating point to fixed point conversion in MALTAB and is now resolved. The followups respon...

5 years ago | 0

Answered
Simulink HDL coder Results compare
If you continue to face the issue please search for Gain block related HDL Coder bug fix by your release here. https://www.math...

5 years ago | 0

Answered
HDL Coder black box inclusion of module with parameterised packed input
>> I considered just using the Bit Concat block and then using the Extract Bits block within the model of the black box, but tha...

5 years ago | 0

Answered
About HDL simulink coder for StateFlow
Attached model describes how to model either edge in Stateflow suitable for HDL code generation. HDL Verision Result C...

5 years ago | 0

Answered
Fixed point to float point conversion of 16 point ifft
See attached example for additional modeling guidelines for MATLAB to HDL.

5 years ago | 0

Answered
Error creading HDL from subsystem
This is a model compilation issue and not HDL Code generation issue. Press ctrl-d or compile the model and make sure there are n...

5 years ago | 0

Answered
HDL Coder: Fails to generate high-level timing support
You have encountered a bug in critical path estimation. However there are no active records with the signature currently active ...

5 years ago | 0

Answered
Create matrix 64x64 that supported by HDL coder
Performing Large Matrix Operation on FPGA web(fullfile(docroot, 'hdlcoder/ug/performing-large-matrix-operation-on-fpga-using-e...

5 years ago | 0

Answered
Define global constant for HDL Coder
Globals are not currently supported in HDL Coder. Use persistent variables instead. Also see this example on how to >> mlhdlc...

5 years ago | 0

Answered
RAM-based shift register in HDL coder
UseRAM parameter: The UseRAM implementation parameter in Simulink HDL block option enables using RAM-based mapping for an intege...

5 years ago | 0

Answered
Implement Reset in Simulink
These page describes how to generate code with synchronous or asynchronous reset. web(fullfile(docroot, 'hdlcoder/ug/reset-and-...

5 years ago | 0

Answered
I want to convert the following code to verilog using hdl coder, please help
The above MATLAB example is poorly written to be taken to HDL code generation. First divide your code into design (DUT) and tes...

5 years ago | 0