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HDL code generation of delay block and problem in regard to the use of verilog ce_out
A sample model would be helpful. I built one using the info shown in the picture above. Given there is a ratio of 5000 bet...

4 years ago | 1

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Answered
In HDL Simulink, How to convert from integer to boolean array.
https://www.mathworks.com/help/hdlcoder/ref/bitslice.html >> hdlcoder_int2bits_bits2int You can check this thread as well....

4 years ago | 0

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HDL supported block for integer to binary
can you try this example? >>hdlcoder_int2bits_bits2int

4 years ago | 0

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Update Diagram fails on "No Connect" Cosim block
Can you share a sample model with your usecase?

4 years ago | 0

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How to deploy matlab deep learning models to Texas Instruments?
DL code generated for library-free “none” target should be deployable on TI C2000. https://www.mathworks.com/videos/generate-...

4 years ago | 0

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Answered
Vivado 2020.2 and HDL coder
HDL Coder generated VHDL/Verilog code is Vivado version independent and works with any version of the Xilinx software. For Viva...

4 years ago | 1

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Answered
Timing Constraint not met error for ZYNQ706
You can consider pipelining the design. See the timing related optimization section in HDL Coder https://www.mathworks.com/help/...

4 years ago | 0

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Numerator of FIR filter using "firpm" command is not working properly for ZYNQ 706
If your Simulink model has a testbench you can consider generating HDL code with the testbench and verify the generated code in ...

4 years ago | 0

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Colon operation in fixed-point
Support for colon exists with fixed-point types according to documentation. https://www.mathworks.com/help/fixedpoint/ref/colon....

4 years ago | 0

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how to fix inferring latch(es) for signal or variable holds its previous value in one or more paths through the process vhdl error
This could be a bug in code generation process. Can you reach out to https://www.mathworks.com/support.html?

4 years ago | 0

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Colon operation in fixed-point
MATLAB HDL Coder workflow does support colon operator during fixed-point conversion and code generation. Please share a sample d...

4 years ago | 0

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SIMPLE HDL code generation example
This example should help do basic LED blinking using a simple counter. Getting Started with Targeting Xilinx Zynq Platform ope...

4 years ago | 0

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Error while generating HDL code from Matlab: Invalid data type. H must be double.
Can you share your design.m, testbench.m files and the project file with necessary settings? Thanks

4 years ago | 0

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Connection Failed in hardware setup
https://www.mathworks.com/support.html Please reach out to support team on this topic.

4 years ago | 0

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i m trying using converting signal processing block into hdl code , but some of the blocks are not compatible into hdl conversion .does anyone knows how to do it
https://www.mathworks.com/help/radar/ug/automotive-adaptive-cruise-control-using-fmcw-and-mfsk-technology.html This example is ...

4 years ago | 0

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error after targheting xilinx Virtex UltraScale+ VCU118.
Possible pilot error in setting up the custom reference design or board support package. Please contact https://www.mathworks.c...

4 years ago | 0

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Why do I receive error Output argument "file_name" (and maybe others) not assigned during call to "mdlAdv_Scripts_Run.get_config_file"
I couldn't find the class/structure mdlAdv_Scripts_Run and method/member get_config_file in HDL Workflow Advisor. Guessing poss...

4 years ago | 0

Answered
HDL IP Core generation for Xilinx Vivado fails since the year turned from 2021 to 2022
HDL IP core generation using Xilinx Vivado fails as of January 1, 2022 (2656440) https://www.mathworks.com/support/bugreports/2...

4 years ago | 1

Answered
Error " Dot indexing is not supported for variable of this type" comes when tried to configure HDL Coder support package for Xilinx Zynq Platform.
MathWorks team is investigating the issue and will provide an update shortly. Any additional reproduction steps are helpful (mac...

4 years ago | 0

Answered
Assertion failed: B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
Here is an example of HDL Coder friendly current control algorithm for your reference. Field-Oriented Control of a Permanent Ma...

4 years ago | 0

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Answered
Assertion failed: B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
This example is not compatible with HDL Code Generation. Reaching to the development team for suggestions on HDL Coder compatibl...

4 years ago | 1

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matlab hdl coder error
See detailed examples of how to perform HDL Code Generation from MATLAB — Examples

4 years ago | 0

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How to build a model that is efficient for HDL conversion?
DVB-S2 HDL PL Header Recovery This example shows how to implement DVB-S2 time, frequency, and phase synchronization and PL head...

4 years ago | 1

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Simulink model not editable
This example shows how to implement a QPSK transmitter and receiver in Simulink® that is optimized for HDL code generation and h...

4 years ago | 0

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HDL Coversion of Simulink code
HDL QPSK Transmitter and Receiver This example shows how to implement a QPSK transmitter and receiver in Simulink® that is opti...

4 years ago | 0

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how to convert matlab code in VHDL ? which tool boxes to download?
You need to partition the MATLAB code into design and testbench files and create a HDL Coder project. Try a sample MATLAB to HD...

4 years ago | 0

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How i can import an existing IP Core in Vivado in Simulink as block?
These links show how to integrate custom RTL code into a model targeted for HDL code generation using HDL Coder https://www.mat...

4 years ago | 0

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HDL coder fails generating wavelet denoise function
Support for C/C++ code generation exists for wdenoise. I have reported the HDL Code Generation request for this function to dev...

4 years ago | 0

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Using std_logic_vector(0 downto 0) in HDL Coder
Unfortunately this coding style switch is not currently available. I have communicated this request with the development team. ...

4 years ago | 0

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error in dlhdl.buildProcessor(hPCNew) step
Can you share the version of MATLAB you are using?

4 years ago | 1