Search results: product_base_code:HD - MATLAB Answers

Filter By

Status Clear

Source Clear

Results for product_base_code:"HDL Coder" (1.228 results)

Results 51 - 100 of 1.228

0

answers

0 votes
2 views

HDL Code Generation using remotely installed Vivado

Asked by Fabio on 12 Feb 2024

Latest activity Commented on by Tom Richter on 12 Feb 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

2

answers

0 votes
6 views

"Unable to check out a license for HDL Coder", even though the tool has that license checked-out

Asked by Douglas Fritz on 29 May 2020

Latest activity Moved by Stefanie Schwarz on 6 Feb 2024

Accepted Answer by Stefan Griebel

MATLAB Installation and Licensing Install Products Introduction to Installation and Licensing

1

answer

0 votes
3 views

Does the Specialized Power Systems toolbox work with HDL workflow advisor

Asked by Andrew Nicholson on 18 Jun 2019

Latest activity Edited by Kiran Kintali on 1 Feb 2024

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

2

answers

2 votes
37 views

what is the difference between FPGA Turnkey and IP Core Generation?

Asked by Yashar on 7 Aug 2015

Latest activity Edited by Kiran Kintali on 29 Jan 2024

Accepted Answer by Wang Chen

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
1 view

How to add MATLAB design, testbench in HDL Coder Project programmatically ?

Asked by Omkar on 24 Jan 2024

Latest activity Edited by akshatsood on 24 Jan 2024

Code Generation

1

answer

0 votes
4 views

How to create a simulink model for testbench

Asked by Edison Gabriel on 21 Jan 2024

Latest activity Commented on by Kiran Kintali on 21 Jan 2024

Code Generation

1

answer

0 votes
3 views

5G NR MIB Recovery Using Xilinx RFSoC Device: Segmentation Fault

Asked by Danna on 26 Oct 2023

Latest activity Commented on by Danna on 21 Jan 2024

Accepted Answer by UDAYA PEDDIRAJU

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
6 views

Error while generating HDL code from Simulink for Canny Edge Detection

Asked by Sushant S on 19 Jan 2024

Latest activity Commented on by Sushant S on 20 Jan 2024

Accepted Answer by Kiran Kintali

FPGA, ASIC, and SoC Development Vision HDL Toolbox Video Formats and Interfaces

1

answer

0 votes
3 views

Transmit and Receive a Tone Using Xilinx RFSoC Device Failed

Asked by Kefayet Ullah on 13 Apr 2022

Latest activity Answered by UDAYA PEDDIRAJU on 20 Jan 2024

FPGA, ASIC, and SoC Development SoC Blockset SoC Blockset Supported Hardware Xilinx Devices Hardware I/O Devices

1

answer

0 votes
0 views

Why do I receive the error "Unable to perform assignment because the left and right sides have a different number of elements." in step 3.2 of HDL Workflow Advisor?

Asked by Gorka Arizkorreta on 16 Jan 2024

Latest activity Answered by Tom Richter on 17 Jan 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx Zynq Platform

1

answer

0 votes
3 views

HDL Coder For Each Subsystem Assertion failed: B:\matlab\src\cgir_hdl\pir_tags\ForEachDataTag.hpp:178:nativeVObj.get()

Asked by Jason Katcha on 15 Jan 2024

Latest activity Commented on by Kiran Kintali on 17 Jan 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder

1

answer

0 votes
6 views

Messy Constellation from the ZCU111 MVDR Beamforming example

Asked by Yang on 24 Nov 2022

Latest activity Answered by UDAYA PEDDIRAJU on 15 Jan 2024

Radar Phased Array System Toolbox Beamforming and Direction of Arrival Estimation Beamforming

1

answer

0 votes
97 views

Troubleshooting connection issues with Xilinx Zynq platform

Asked by MathWorks Support Team on 3 Jul 2018

Latest activity Edited by MathWorks Support Team on 12 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation Embedded Coder Deployment, Integration, and Supported Hardware Embedded Coder Supported Hardware Intel SoC Devices

0

answers

0 votes
3 views

SoC Builder Error: The specified key is not present in this container.

Asked by Vu Hoang Thang Chau on 11 Dec 2023

Latest activity Commented on by Vu Hoang Thang Chau on 10 Jan 2024

FPGA, ASIC, and SoC Development SoC Blockset System on Chip (SoC)

2

answers

0 votes
24 views

HDL Coder to / downto order

Asked by Michael Felger on 13 Nov 2019

Latest activity Edited by Kiran Kintali on 9 Jan 2024

Accepted Answer by Kiran Kintali

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

1

answer

0 votes
2 views

FIL I/O options missing in the FIL wizard.

Asked by Charanraj Mohan on 13 Nov 2023

Latest activity Commented on by Charanraj Mohan on 8 Jan 2024

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

0 votes
3 views

wait statement without UNTIL clause not supported for synthesis Error when using HDL coder

Asked by Aswin PJ on 18 Mar 2016

Latest activity Edited by Kiran Kintali on 6 Jan 2024

Code Generation HDL Coder

2

answers

0 votes
26 views

How can I use a custom board with the Zynq workflow provided by MATLAB/Simulink?

Asked by MathWorks Support Team on 17 Jul 2021

Latest activity Answered by fgao on 5 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder Targeting FPGA & SoC Hardware

3

answers

0 votes
30 views

Function is not defined for values of class embedded.fi when using HDL coder

Asked by Sam on 2 Apr 2013

Latest activity Answered by Bharath Venkataraman on 5 Jan 2024

Accepted Answer by Tim McBrayer

Code Generation HDL Coder

4

answers

0 votes
74 views

How can I convert MATLAB Code to VHDL Code?

Asked by Sabarinathan Vadivelu on 8 Mar 2013

Latest activity Answered by Bharath Venkataraman on 5 Jan 2024

Accepted Answer by TAB

Code Generation HDL Coder

2

answers

0 votes
3 views

HDL Coder throws error "Minimize algebraic loop occurrences" not supported on atomic subsystem '...' for HDL code generation" when the option is disabled

Asked by Eirik Nordeng on 18 Dec 2023

Latest activity Answered by Eirik Nordeng on 4 Jan 2024

Accepted Answer by Swaraj

Simulink Simulink Environment Fundamentals Block Libraries Ports and Subsystems

1

answer

0 votes
3 views

In R2018a, how can I force HDL Coder to generate HDL code for a lookup table to use RAM or Block RAM?

Asked by MathWorks Support Team on 16 Aug 2018

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder

1

answer

0 votes
1 view

How can I modify the HDL Compilation commands when doing cosimulation using the Cosimulation Wizard?

Asked by MathWorks Support Team on 23 Jul 2018

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder

2

answers

0 votes
5 views

When using the HDL Workflow Advisor, why do I get errors in Task 1.2 that mention "Dot indexing is not support for variables of this type"?

Asked by MathWorks Support Team on 18 Sep 2019

Latest activity Edited by MathWorks Support Team on 3 Jan 2024

Accepted Answer by MathWorks Support Team

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

0

answers

0 votes
7 views

CCSDS TM HDL Receiver implemenation in Zed board.

Asked by VISHNU on 23 Dec 2023

Latest activity Commented on by Kranti Balaga on 28 Dec 2023

Code Generation

1

answer

0 votes
10 views

SystemC code generation directly from SIMULINK model

Asked by John Terry on 24 Dec 2023

Latest activity Commented on by Bhanu on 27 Dec 2023

Code Generation HDL Verifier ASIC Testbench Transaction Level Model Generation

1

answer

0 votes
4 views

Delay in MATLAB Function block

Asked by 悠矢 on 21 Dec 2023

Latest activity Moved by Angelo Yeo on 25 Dec 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
5 views

Assertion Error in HDL Coder

Asked by 悠矢 on 21 Dec 2023

Latest activity Commented on by 悠矢 on 25 Dec 2023

Code Generation HDL Coder

2

answers

0 votes
2 views

Multiple IOSTANDARDs for a single HDL coder interface

Asked by Øystein Buanes on 20 Dec 2023

Latest activity Answered by JT Ferrara on 22 Dec 2023

Accepted Answer by JT Ferrara

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
1 view

How to avoid the error "hp2f does not support matrix types on its ports for HDL code"?

Asked by MathWorks Support Team on 22 Nov 2023

Latest activity Answered by MathWorks Support Team on 20 Dec 2023

Accepted Answer by MathWorks Support Team

FPGA, ASIC, and SoC Development Vision HDL Toolbox HDL Code Generation and Deployment

1

answer

0 votes
9 views

Generating math expression LUT using variable from workspace

Asked by Eirik Nordeng on 20 Dec 2023

Latest activity Answered by Andy Bartlett on 20 Dec 2023

Accepted Answer by Andy Bartlett

Simulink Modeling Configure Signals, States, and Parameters Data Types

3

answers

0 votes
5 views

Generic data type configuration based on reference precision.

Asked by Eirik Nordeng on 4 Dec 2023

Latest activity Answered by Eirik Nordeng on 19 Dec 2023

Code Generation HDL Coder HDL Code Generation from Simulink Speed and Area Optimization Speed Optimization

2

answers

0 votes
2 views

Lane Detection with Zynq-Based Hardware - Pixel-Stream Model

Asked by Krishnent Sanal Kumar on 21 Jun 2018

Latest activity Answered by Eric Cigan on 18 Dec 2023

Accepted Answer by Bharath Venkataraman

Image Processing and Computer Vision Computer Vision Toolbox Computer Vision Toolbox Supported Hardware

1

answer

0 votes
7 views

How to use hardware mapping with the RFDC Bus creator block for the SOC builder?

Asked by Jim Esmond on 29 Nov 2022

Latest activity Answered by SANKALP DEV on 15 Dec 2023

FPGA, ASIC, and SoC Development SoC Blockset SoC Blockset Supported Hardware Xilinx Devices Hardware I/O Devices

2

answers

0 votes
0 views

whether regressionenseblepredict block can be used in hdl coder?

Asked by Nandhu mol M. V on 20 Jun 2023

Latest activity Answered by Hamid Satarboroujeni on 14 Dec 2023

FPGA, ASIC, and SoC Development

1

answer

0 votes
3 views

Problem with HDL code generation of Regression Ensemble Predict block using Simulink and HDL coder

Asked by Neeraja on 20 Jun 2023

Latest activity Answered by Hamid Satarboroujeni on 14 Dec 2023

AI, Data Science, and Statistics Statistics and Machine Learning Toolbox Regression Support Vector Machine Regression

0

answers

0 votes
0 views

Under Reference design parameters, there is ethernet interface instead of JTAG connection .

Asked by Prashanthi Pathipati on 11 Dec 2023

Code Generation HDL Coder

1

answer

0 votes
6 views

HDL FIFO Reset Problem

Asked by Juan Martin de las mulas on 1 Dec 2023

Latest activity Commented on by Juan Martin de las mulas on 11 Dec 2023

Code Generation HDL Coder

2

answers

0 votes
9 views

Xilinx ZCU111 OFDM example doesn't load

Asked by Yaddehi De Silva on 2 Jun 2021

Latest activity Answered by Souta on 6 Dec 2023

Code Generation HDL Coder Targeting FPGA & SoC Hardware

1

answer

0 votes
7 views

adi rf som gpio options

Asked by Raz Elimelech on 3 Dec 2023

Latest activity Commented on by Raz Elimelech on 6 Dec 2023

Accepted Answer by Tom Richter

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
13 views

Using a persistent variable array in MATLAB function for HDL Coder

Asked by Kaan on 5 Dec 2023

Latest activity Answered by Tom Richter on 5 Dec 2023

Code Generation

1

answer

0 votes
11 views

Task "Vivado IP Packager" unsucessful in Matlab 2022 b, Vivado 2022.2 cannot generate HDL code

Asked by Yongjie on 10 Nov 2023

Latest activity Edited by Siraj on 5 Dec 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
8 views

HDL Optimized FFT Does Not Yield the Same Results As FFT

Asked by Kaan on 20 Nov 2023

Latest activity Commented on by Bharath Venkataraman on 29 Nov 2023

Signal Processing DSP System Toolbox Transforms and Spectral Analysis Transforms

1

answer

0 votes
2 views

Using Custom I/Q Sample on "GPS HDL Acquisition and Tracking Using C/A Code" Example

Asked by Kaan on 22 Nov 2023

Latest activity Answered by Tom Richter on 24 Nov 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
4 views

dsp.Window future removal - future replacements?

Asked by Joshua Ford on 10 May 2022

Latest activity Answered by Nihal on 23 Nov 2023

Code Generation Embedded Coder Deployment, Integration, and Supported Hardware Embedded Coder Supported Hardware Texas Instruments C2000 Processors

1

answer

0 votes
9 views

Simulink crashes very often during normal work

Asked by Eirik Nordeng on 21 Nov 2023

Latest activity Edited by Fangjun Jiang on 22 Nov 2023

Code Generation Fixed-Point Designer

1

answer

0 votes
2 views

Real-time data exchange of Simulink and Zynq-7000

Asked by Armin Lensker on 1 Mar 2018

Latest activity Commented on by Sam on 16 Nov 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
13 views

ALTERA DE0-NANO Board Support for HDL Coder

Asked by shauk on 18 Apr 2017

Latest activity Commented on by Ivan Kolesnikov on 14 Nov 2023

Accepted Answer by Ankit Bhardwaj

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

1

answer

0 votes
4 views

Task "Vivado IP Packager" unsucessful in 2023, cannot generate HDL code

Asked by Emily on 17 Aug 2023

Latest activity Commented on by Yongjie on 10 Nov 2023

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

2

answers

5 votes
79 views

HDL IP Core generation for Xilinx Vivado fails since the year turned from 2021 to 2022

Asked by MathWorks HDL Coder Team on 4 Jan 2022

Latest activity Commented on by Yongjie on 10 Nov 2023

Accepted Answer by MathWorks HDL Coder Team

Code Generation HDL Coder HDL Coder Supported Hardware Xilinx FPGA and SoC Devices

Results 51 - 100 of 1.228

Filter By

Status Clear

Source Clear

Category Clear

0

2

1

2

1

1

1

1

1

1

1

1

1

0

2

1

2

2

3

4

2

1

1

2

0

1

1

1

2

1

1

3

2

1

2

1

0

1

2

1

1

1

1

1

1

1

1

1

1

2