Errore fase di build soc builder

Ho creato un modello simulink in cui ho realizzato un SoC con fpga, memoria e processore. Nella fase di build mi da errore dicendomi che il blocco Stream Read (presente nel modello del processore in lettura) non è collegato al blocco AXI4-Stream to Software presente nel modello top_level. Come si può vedere nella foto sotto il collegamento però c'è quindi non riesco a capire da cosa è dovuto il problema.

Grazie e buona giornata.

[John D'Errico]

Google translate:

I have created a Simulink model in which I implemented an SoC comprising an FPGA, memory, and a processor. During the build phase, I encountered an error indicating that the Stream Read block (located within the processor model for read operations) is not connected to the AXI4-Stream to Software block found in the top-level model. However, as can be seen in the image below, the connection is indeed present; therefore, I am unable to determine the cause of the problem.

Thank you, and have a good day.

Answer 1

[Adarsh]

Hi @Leonardo,

I understand you are encountering a build error indicating that the Stream Read block inside the processor model is not connected to the AXI4-Stream to Software block at the top level, even though the connection appears to be present in the model diagram.

This type of error typically occurs when the signal routing is not properly propagated through the subsystem boundaries. The connection may appear correct at the top level, but the signal from the AXI4-Stream to Software block needs to be correctly routed through input ports into the processor subsystem, with the Stream Read block connected to the corresponding inport block inside.

Another common cause is when there are additional subsystem layers between the top level and the Stream Read block. Each intermediate level must correctly pass the signal through without breaking the connection chain.

Additionally, mismatched block parameters might cause Simulink to report the blocks as disconnected during compilation. Both the AXI4-Stream to Software block and the Stream Read block must have compatible settings.

To resolve this issue, please verify the following:

• Check that the AXI4-Stream to Software block output connects to an inport of the processor subsystem
• Confirm the inport inside the processor subsystem connects directly to the Stream Read block
• If multiple subsystem layers exist, trace the signal path through each level to ensure continuous connectivity
• Verify the data type and width settings match between the AXI4-Stream to Software block and Stream Read block
• Ensure the sample time configuration is compatible between both blocks
• Check that the stream format settings are identical in both block parameters

For more information the following MATLAB documenatation can be referred:

https://www.mathworks.com/help/soc/ref/axi4streamtosoftware.html

I hope this helps!