Why do I get the error: " FIL cosimulation failed: the output does not match the expeced result" when I run FPGA-in-the-Loop Test?

Hi, iI m trying to run the fpga in the loop test inside HDL coder. The HDL code was generated by a script in matlab (I didn't use a model in Simulink). I selected the board Xilinx Virtex Ultrascale VCU118 and the connection is JTAG ( my board has an onboard Digilent USB-JTAG module) . Then I added Vivado tool to MATLAB search path. When I tried to validate FPGA board, I obtain this error: "FIL cosimulation failed: the output does not match the expeced result ".

How can I fix it? Thank you.

[YP]

FPGA-in-the-Loop test will use a simple unit delay as DUT. It doesn't depend on customer's HDL code. We currently don't has VCU118 on site to reproduce. To rule out the possibility of board setup issues, you may either try PCIe on VCK118 or try JTAG FIL on another FPGA board (if it is available).

[AriF]

I will try to use the PCIe on my board. Thank you!

Answer 1

[Kiran Kintali]

If the HDL Code you are running is run with is generated from HDL Coder and is not matching the MATLAB or Simulink testbench then this is not an expected message. You can contact technical support with reproduction steps.