Controller HIL Testing of Power Factor Correction Converter

This example uses:

This example demonstrates how to model and simulate a high-fidelity power factor correction (PFC) converter digital twin (including switching dynamics and faults), implement fixed-point designs for FPGA runtime efficiency, set up a hardware-in-the-loop (HIL) test system to test PFC controllers on target hardware, and follow an integrated workflow from controls design to real-time verification.

Note

The model in this example is tested and shipped by Speedgoat®. For more information, see Controller HIL Testing of Power Factor Correction Converter example.

Speedgoat Products

  • Performance Real-Time Target Machine

  • IO334 Simulink®-Programmable FPGA I/O Module

  • IO3XX-21: I/O Interface Extension with 56 TTL lines

  • Launchpad Development Kit

  • HDL Coder™ Integration Packages

  • Motion Control HDL I/O Blockset

MathWorks Products

  • Simulink Real-Time™

  • C2000™ Microcontroller Blockset

  • Simscape™ Electrical™

See Also

External Websites