ARM Cortex-M4 - Ethernet - MATLAB & Simulink

Enable DHCP for local IP address assignment

Select this parameter to configure the board to get an IP address from the local DHCP server on the network.

You can get to know the dynamical assigned IP address through DHCP from the build log shown in the diagnostic viewer.

Local IP Address

Select this parameter to set the IP address of the board.

Set the board IP address according to these guidelines:

The subnet address, typically the first 3 bytes of the board IP address, must be the same as the first 3 bytes of the host IP address.
The last byte of the board IP address must be different from the last byte of the host IP address.
The board IP address must not conflict with the IP addresses of other computers. For example, if the host IP address is 192.168.8.2, then you can use 192.168.8.3, if available.

Subnet mask

Specify the subnet mask for the board. The subnet mask is a mask that designates a logical subdivision of a network.

The value of the subnet mask must be the same for all devices on the network.

Gateway

Set the serial gateway to the gateway required to access the target computer.

For example, when you set this parameter to 255.255.255.255, it means that you do not use a gateway to connect to your target computer. If you connect your computers with a crossover cable, leave this property as 255.255.255.255.

If you communicate with the target computer from within your LAN, you do not need to change this setting.
If you communicate from a host located in a LAN different from your target computer (especially via the Internet), you must define a gateway and specify its IP address in this parameter.

MAC Address

Specify the media access control (MAC) address, the physical network address of the board.

Under most circumstances, you do not need to change the MAC address. If you connect more than one board to a single computer so that each address is unique, change the MAC address. You must have a separate network interface card (NIC) for each board.

To change the MAC address, specify an address that is different from the address that belongs to any other device attached to your computer. To obtain the MAC address for a specific board, refer to the label affixed to the board or consult its documentation.

The MAC address must be in the six octet format. For example, DE-AD-BE-EF-FE-ED

Ethernet clock speed in Mbps: The Ethernet clock runs at 25 MHz, which supports 10 Mbps or 100 Mbps Ethernet speeds on TI C28x devices. It is created by dividing AUXPLLRAWCLK or SYSPLLRAWCLK by (ETHDIV + 1) to get exactly 25 MHz for reliable communication with the PHY.

Ethernet clock source selection (Ethernet clock calculated in CPU1 should be 100 MHz for internal clock and 100 Mbps speed): To achieve 100 Mbps Ethernet speed on supported C28x MCUs (e.g., F2838x series) with integrated EMAC, configure the input clock to 100 MHz and set the Ethernet clock divider (ETHDIV) to produce a 50 MHz reference clock for the RMII interface. The EMAC module internally doubles this 50 MHz clock to 100 MHz for full-speed data transfer. By default, the Ethernet clock source selection (Ethernet clock calculated in CPU1 should be 100 MHz for internal clock and 100 Mbps speed) is set to Internal clock.

Carrier sense signal pin (ENET_MII_CRS): Select the corresponding GPIO pin number for carrier sense input. The ENET_MII_CRS pin is the carrier sense input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY asserts this pin high when it detects carrier activity on the network medium, enabling the EMAC to defer transmission in half-duplex mode to avoid collisions (CSMA/CD).

Collision detection signal pin (ENET_MII_COL): Select the corresponding GPIO pin number for collision detect input. The ENET_MII_COL pin is the collision detect input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when using MII mode. The PHY asserts this pin high upon detecting a collision (simultaneous transmission by two devices), enabling the EMAC to abort the current frame and perform backoff/retransmission according to the CSMA/CD protocol in half-duplex operation.
Transmit clock signal pin (ENET_MII_TX_CLK): The ENET_MII_TX_CLK pin is the transmit clock input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY drives this pin with a 25 MHz clock signal (for 10 Mbps) or 2.5 MHz (for 100 Mbps), which the EMAC uses to synchronize the transmission of data and control signals (TX_EN, TXD[3:0], TX_ER) to the PHY in half-duplex or full-duplex operation.

Receive clock signal pin (ENET_MII_RX_CLK): The ENET_MII_RX_CLK pin is the receive clock input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY drives this pin with a 25 MHz clock signal (for 10 Mbps) or 2.5 MHz (for 100 Mbps), which the EMAC uses to synchronize the reception of incoming data and control signals (RX_DV, RXD[3:0], RX_ER) from the PHY during half-duplex or full-duplex operation.

Transmit enable signal pin (ENET_MII_TX_EN): The ENET_MII_TX_EN pin is the transmit enable output from the EMAC module to the external Ethernet PHY on supported C28x MCUs when operating in MII mode. The EMAC asserts this pin high to indicate that valid transmit data (TXD[3:0]) and control signals are present on the MII interface, instructing the PHY to begin transmitting the Ethernet frame onto the network medium during half-duplex or full-duplex operation.

Receive data valid signal pin (ENET_MII_RX_DV): The ENET_MII_RX_DV pin is the receive data valid output from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY asserts this pin high to indicate that valid receive data (RXD[3:0]) and associated control signals are present on the MII interface, allowing the EMAC to sample and process incoming Ethernet frames during reception in half-duplex or full-duplex operation.

Transmit error signal pin (ENET_MII_TX_ERR): The ENET_MII_TX_ERR pin is the transmit error output from the EMAC module to the external Ethernet PHY on supported C28x MCUs when operating in MII mode. The EMAC asserts this pin high during frame transmission to signal an error condition (e.g., underrun, late collision, or excessive deferral), instructing the PHY to corrupt the frame by sending an invalid symbol sequence, ensuring the receiving station detects and discards the faulty packet in half-duplex or full-duplex operation.

Receive error signal pin (ENET_MII_RX_ERR): The ENET_MII_RX_ERR pin is the receive error output from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY asserts this pin high during frame reception to signal an error condition (e.g., CRC error, alignment error, or dribble bits), allowing the EMAC to detect and discard the faulty frame in half-duplex or full-duplex operation.

Transmit data bit 0 pin (ENET_MII_TX_DATA0): The ENET_MII_TX_DATA0 pin is the least significant bit (bit 0) of the transmit data bus output from the EMAC module to the external Ethernet PHY on supported C28x MCUs when operating in MII mode. The EMAC drives this pin with the serial transmit data (TXD[0]) synchronized to the TX_CLK, allowing the PHY to reconstruct the Ethernet frame bits during transmission in half-duplex or full-duplex operation (TXD[3:0] collectively carry 4 bits per clock cycle).

Receive data bit 0 pin (ENET_MII_RX_DATA0): The ENET_MII_RX_DATA0 pin is the least significant bit (bit 0) of the receive data bus input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY drives this pin with the serial receive data (RXD[0]) synchronized to the RX_CLK, allowing the EMAC to reconstruct incoming Ethernet frame bits during reception in half-duplex or full-duplex operation (RXD[3:0] collectively carry 4 bits per clock cycle).

Transmit data bit 1 pin (ENET_MII_TX_DATA1): The ENET_MII_TX_DATA1 pin is bit 1 of the transmit data bus output from the EMAC module to the external Ethernet PHY on supported C28x MCUs when operating in MII mode. The EMAC drives this pin with the second bit of the serial transmit data (TXD[1]), synchronized to the TX_CLK, allowing the PHY to reconstruct the Ethernet frame (TXD[3:0] collectively carry 4 bits per clock cycle) during transmission in half-duplex or full-duplex operation.

Receive data bit 1 pin (ENET_MII_RX_DATA1): The ENET_MII_RX_DATA1 pin is bit 1 of the receive data bus input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY drives this pin with the second bit of the serial receive data (RXD[1]), synchronized to the RX_CLK, allowing the EMAC to reconstruct incoming Ethernet frame bits (RXD[3:0] collectively carry 4 bits per clock cycle) during reception in half-duplex or full-duplex operation.

Transmit data bit 2 pin (ENET_MII_TX_DATA2): The ENET_MII_TX_DATA2 pin is bit 2 of the transmit data bus output from the EMAC module to the external Ethernet PHY on supported C28x MCUs when operating in MII mode. The EMAC drives this pin with the third bit of the serial transmit data (TXD[2]), synchronized to the TX_CLK, allowing the PHY to reconstruct the Ethernet frame (TXD[3:0] collectively carry 4 bits per clock cycle) during transmission in half-duplex or full-duplex operation.

Receive data bit 2 pin (ENET_MII_RX_DATA2): The ENET_MII_RX_DATA2 pin is bit 2 of the receive data bus input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY drives this pin with the third bit of the serial receive data (RXD[2]), synchronized to the RX_CLK, allowing the EMAC to reconstruct incoming Ethernet frame bits (RXD[3:0] collectively carry 4 bits per clock cycle) during reception in half-duplex or full-duplex operation.

Transmit data bit 3 pin (ENET_MII_TX_DATA3): The ENET_MII_TX_DATA3 pin is bit 3 (most significant bit) of the transmit data bus output from the EMAC module to the external Ethernet PHY on supported C28x MCUs when operating in MII mode. The EMAC drives this pin with the fourth bit of the serial transmit data (TXD[3]), synchronized to the TX_CLK, allowing the PHY to reconstruct the Ethernet frame (TXD[3:0] collectively carry 4 bits per clock cycle) during transmission in half-duplex or full-duplex operation.

Receive data bit 3 pin (ENET_MII_RX_DATA3): The ENET_MII_RX_DATA3 pin is bit 3 (most significant bit) of the receive data bus input from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY drives this pin with the fourth bit of the serial receive data (RXD[3]), synchronized to the RX_CLK, allowing the EMAC to reconstruct incoming Ethernet frame bits (RXD[3:0] collectively carry 4 bits per clock cycle) during reception in half-duplex or full-duplex operation.

Management data clock pin (ENET_MDIO_CLK): The ENET_MDIO_CLK pin is the management data clock output from the EMAC module to the external Ethernet PHY on supported C28x MCUs. The EMAC drives this pin with a clock signal (typically 1–2.5 MHz, derived from the system clock) to synchronize bidirectional data transfers over the MDIO interface, enabling the EMAC to read and write configuration registers in the PHY (e.g., speed, duplex mode, link status) during initialization and runtime operation.

Management data I/O pin (ENET_MDIO_DATA): The ENET_MDIO_DATA pin is the bidirectional management data input/output signal between the EMAC module and the external Ethernet PHY on supported C28x MCUs. The EMAC drives this pin to send configuration commands and register write data to the PHY, while the PHY drives it to return register read data, enabling the EMAC to configure and monitor PHY settings (e.g., speed, duplex mode, link status) over the standard MDIO interface synchronized to the management data clock (ENET_MDIO_CLK).

Pulse per second output 0 pin (ENET_PPS0): The ENET_PPS0 pin is the Pulse Per Second (PPS) output signal from the EMAC module on supported C28x MCUs with integrated Ethernet MAC. The EMAC generates a precise 1 Hz pulse (typically 100 ms wide) on this pin, synchronized to the PTP (Precision Time Protocol) grandmaster clock or an internal reference, enabling time synchronization with external devices, GPS modules, or other networked systems for applications requiring sub-microsecond accuracy.

Pulse per second output 1 pin (ENET_PPS1): The ENET_PPS1 pin is the second Pulse Per Second (PPS) output signal from the EMAC module on supported C28x MCUs with integrated Ethernet MAC. The EMAC generates a precise 1 Hz pulse (typically 100 ms wide) on this pin, synchronized to the PTP (Precision Time Protocol) grandmaster clock or an internal reference, providing an additional timing reference for external devices, GPS modules, or networked systems requiring sub-microsecond synchronization in applications such as distributed control or data acquisition.

MII Interrupt Signal Pin (ENET_MII_INTR): The ENET_MII_INTR pin is the interrupt output from the external Ethernet PHY to the EMAC module on supported C28x MCUs when operating in MII mode. The PHY asserts this pin (typically active low) to signal events such as link status change, auto-negotiation complete, or error conditions, allowing the EMAC to trigger an interrupt to the CPU for handling PHY management tasks without constant polling.

ARM Cortex-M4 - Ethernet

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