Interprocess Data Channel

Model interprocessor data channel between two processors

Since R2020b

• 

Libraries:
SoC Blockset / Processor Interconnect
C2000 Microcontroller Blockset / Test Bench Blocks
Embedded Coder Support Package for Infineon AURIX TC3x Microcontrollers / Test Bench Blocks
Embedded Coder Support Package for Infineon AURIX TC4x Microcontrollers / Test Bench Blocks

Description

The Interprocess Data Channel block simulates the interprocessor data channel available in multiprocessor or OS managed SoC hardware board families. The block provides a channel for asynchronous data transfer between two processors. This diagram shows a generalized view of the interprocessor data connection.

Note

If you are using multiprocessor modeling approach with single model triggering multiple cores using Task manager, use the Interprocess Data Read and Interprocess Data Write blocks to send and receive data between cores.

Use IPC Receive and IPC Transmit blocks to receive or sent data to either core for multi-core processors. Use these blocks for flat model approach where you are using separate models for each core.

To help you choose the right solution for your application, see Communication Between Cores Using IPC Blocks for the detailed comparison between the IPC Transmit/Receive blocks and Interprocess Data Read/Write blocks.

Examples

One Way Interprocess Communication

One-way interprocess data communication between two bare metal processors.

(SoC Blockset)

Two Way Interprocess Communication

Two-way interprocess data communication between two processors running in an operating system managed processor.

(SoC Blockset)

Partition Motor Control for Multiprocessor MCUs

Partition real-time motor control application on to multiple processors to achieve design modularity and improved control performance.

• Open Model

Limitations

In an SoC model, when Interprocess Data Channel blocks form a closed-loop between two or more tasks, it can create an artificial algebraic loop for the Simulink^® solver. To break the loop, the Simulink solver implicitly adds a delay into the loop. This delay is related to an internal event and cannot be modified by the user, but the delay typically will be on the same order as the base time-step of the model. For more information on artificial algebraic loops in Simulink solvers, see Artificial Algebraic Loops.

Ports

Input

datain — Input data message

scalar

This message port receives input data as a message from a connected Interprocess Data Write block. For more information on messages, see Messages.

Data Types: SoCData

Output

dataout — Output data message

scalar

This message port sends output data as a message to a connected Interprocess Data Read block. For more information on messages, see Messages.

Data Types: SoCData

overwritten — Output overwrite notification signal

scalar

This port sends a true signal output whenever an overwrite of the internal buffer queue occurs. When the connected processor model executes in external mode, the connected Interprocess Data Write block generates the overwritten signal in the Simulation Data Inspector tool.

Dependencies

To enable this port, select the Show when buffer is overwritten parameter.

Data Types: Boolean

used — Output number of buffers in use

scalar

This port outputs the number of buffers currently in use in the block's internal buffer queue. When the connected processor model executes in external mode, the connected Interprocess Data Write block generates the used signal in the Simulation Data Inspector tool.

Dependencies

To enable this port, select the Show number of used buffers parameter.

Data Types: Boolean

event — Task event signal

scalar

This port sends a task event signal that triggers the Task Manager block to execute the associated event-driven task.

Note

• If one Interprocess Data Channel block is in the model, then only IPC0 interrupt is allowed

• If two Interprocess Data Channel blocks are in the model, the only IPC0 and IPC1 interrupts are allowed.

Dependencies

To enable this port, select the Show event port parameter.

Data Types: rteEvent

Parameters

Main

Circular FIFO depth — Number of storage buffers

1 (default) | positive integer

Buffers are circular buffers created in shared message RAM. Number of buffer is the number of elements stored at a time in the shared message RAM. These are not FIFO but will be overwritten at next instance.

Propagation delay — Propagation delay of data through the channel

1e-6 (default) | non-negative number

Specify the propagation delay of data transfers through the this block. To ignore propagation delays, set this parameter to 0.

Show event port — Option to enable task event ports

off (default) | on

Enable an event port that, when connected to the Task Manager block, can execute event-driven tasks.

Statistics

Show number of used circular FIFO — Option to enable circular FIFO count ports

off (default) | on

Enable an output port that shows the current number of circular FIFO used in the Interprocess Data Channel block internal buffer queue.

Show when circular FIFO is overwritten — Enable port that shows circular FIFO overwrites

off (default) | on

Enable an output port that signals when an overwrite of the Interprocess Data Channel block internal circular FIFO queue occurred.

Version History

Introduced in R2020b