This example shows how to implement and verify a design on Xilinx® RFSoC device using SoC Blockset®. You will deploy a system on Xilinx RFSoC Evaluation kits that generates a sinusoidal tone from an FPGA, transmits it across multiple RF channels and receives it back into the device to complete the loopback. For modeling and simulation of the system, see the Transmit and Receive a Tone Using Xilinx RFSoC Device - Part 1 System Design example.
Supported Hardware Platforms:
Xilinx® Zynq UltraScale®+ ZCU111 evaluation kit + XM500 Balun card
Xilinx® Zynq UltraScale®+ ZCU216 evaluation kit + XM655 Balun card
Hardware Setup for ZCU111 kit
Connect the SMA connectors on the XM500 Balun card to complete the loopback between the DACs and ADCs, according to the connections provided in the following table. Use DC blocks for differential channels loopback.
To implement the model
soc_rfsoc_datacapture on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board option is set to
Xilinx® Zynq UltraScale+(R) ZCU111 evaluation kit on the System on Chip tab of the Simulink toolstrip.
To open SoC Builder, click the Configure, Build, & Deploy button. After the SoC Builder tool opens, follow these steps:
Select 'Build Model' on the 'Setup' screen. Click 'Next'.
Click 'View/Edit Memory Map' to view the memory map on 'Review Memory Map' screen. Click 'Next'.
Specify the project folder on 'Select Project Folder' screen. Click 'Next'.
Select 'Build External mode' on the 'Select Build Action' screen. Click 'Next'.
Click 'Validate' to check the compatibility of the model for implementation on the 'Validate Model' screen. Click 'Next'.
Click 'Build' to begin building of the model on the 'Build Model' screen. An external shell opens when FPGA synthesis begins. Click 'Next'.
Click 'Test Connection' on 'Connect Hardware' screen to test the connectivity of the host computer with SoC board. Click 'Next' to go to 'Run Application' screen.
The FPGA synthesis may take more than 30 minutes to complete. To save time, you can use the provided pregenerated bitstream by following these steps.
Close the external shell to terminate synthesis.
Copy the pregenerated bitstream to your project folder by entering this command at the MATLAB command prompt.
Click 'Load and Run' button to load pregenerated bitstream and run the model on the SoC board.
After the bit file is loaded, open the generated software model, copy the spectrum analyzer and scope from the top model and connect to the rate transition block as shown in this figure, and run the model. You can observe the tone frequency of the ADC channel 1 default in the spectrum analyzer.
Run the model in external mode and verify that the received tone is at 0.5 MHz on the Spectrum Analyzer. By default, ADC channel 1 is configured for visualization. To select a different ADC channel, modify the
adcChannelSelect parameter. The tone signal as transmitted through various DAC channels is scaled differently. This is seen as the difference in the peak value for the received tone in the spectrum scope. For instance, running the model with
adcChannelSelect parameter value of 5 (corresponding to Channel 5) results in a lower peak on the Spectrum Analyzer when compared with Channel 1.
Note: You will not see any output in Channel 3 and Channel 4 on the XM500 Balun card. These channels support 1 to 4 GHz range, which is above the transmitted tone of 0.5 MHz.
Implement and run on ZCU216 hardware
Hardware setup: Connect the XM655 Balun card and complete the loopback between the DACs and ADCs as shown in table.
To implement the model
soc_rfsoc_IQ_datacapture_top on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board option is set to
Xilinx® Zynq UltraScale+(R) ZCU216 evaluation kit on the System on Chip tab of the Simulink toolstrip. and follow the same socBuilder steps defined in above section, but to load the pregenerated bitstream use the below command for ZCU216 evaluation kit.
Run the software model in external mode and verify that the received tone is at 0.5 MHz on the Spectrum Analyzer.
You can profile the execution of processor task durations using on-device profiling features of SoC Blockset. This tool is useful to debug and verify that the tasks are completed in a timely manner with the data received asynchronously from the FPGA.
To enable the processor task profiling, open the Configuration Parameter dialog box in generated software model and select Hardware Implementation > Hardware Board settings > Task Profiling on processor. Select Show on SDI and then select Save to file.
Set Instrumentation to code. Set the simulation stop time to 10 seconds and run the model in the external mode. After simulation is completed, open the Simulation Data Inspector (SDI), navigate to the latest run, and add a signal DataReadTask to the plot. From the plot you can observe the frame rate as 2 milliseconds.
This example demonstrated how to implement a wireless design by including the RF Data Converter on the Xilinx RFSoC device. Using SoC Builder, you implemented a system that generated a tone from the FPGA and performed the loopback through the RF Data Converter block. You verified that the system worked as expected on the hardware.