Configure the PLL and sampling rate of DAC tile
configures the source and reference clock of the phase-locked loop (PLL) and sampling rate
of the specified DAC tile.
rfDataConverter — RF data converter
RF data converter, specified as an
object. Via Ethernet, this object connects the host computer to the RF data converter on
the connected SoC device. Use the object functions and properties of this object to
configure the RF data converter.
tileId — Identifier of RF-DAC tile
Identifier of the RF-DAC tile connected to the programmable logic, specified as
3. Available options for the RF-DAC tile ID vary according to the
specified RFSoC device. A tile contains several DACs, accessible as channels, and
several shared timing units, including a clock and PLL.
PLLSrc — Source clock signal of the PLL
Source clock signal of the PLL in the RF-DAC tile, specified as
"External LMK/LMX". The source
clock signal can come from either the clock in the tile or the external source.
PLLRefClk — Frequency of reference clock to PLL
Frequency of the reference clock to the PLL, specified as a positive scalar. This reference clock frequency drives the PLL in the RF-DAC tile.
samplingRate — Sampling rate
Sampling rate in MHz, specified as a positive scalar.
Introduced in R2020b