HDL Coder™ Support Package for Xilinx® RFSoC Devices enables generation of IP cores that can integrate into RFSoC devices using Xilinx Vivado® Design Suite.
This support package includes reference designs for popular RFSoC development kits, so you can generate HDL code and port mappings to I/O and AXI registers to interface with RF tiles and DDR memory, and interactively control the FPGA design from MATLAB®.
You can use SoC Blockset™ for system-level modeling of RFSoC devices, configuration of custom RFSoC-based boards, and deployment of complete SoC applications, including executables for ARM® Cortex®-A53 processors.
Download and install support package for use with third-party EDA tools and supported hardware
Capture data to MATLAB or Simulink from RFSoC devices
Read and write data to PL-DDR4 memory
Polyphase channelizer and multi-tile synchronization (MTS) examples
Configure RF data converter on RFSoC device from MATLAB