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Xilinx FPGA Board Support from HDL Verifier

HDL Verifier™ automates the verification of HDL code on FPGA boards by providing connections between your FPGA board and your simulations in Simulink® or MATLAB®.

  • FPGA-in-the-loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an FPGA board.

  • FPGA data capture is a way to observe signals from your design while the design is running on the FPGA. It captures a window of signal data from the FPGA, based on your configuration and trigger settings, and returns the data to MATLAB or Simulink.

  • MATLAB AXI master provides access to live on-board memory locations from MATLAB. You must include the MATLAB AXI master IP in your FPGA design.

To use each of these features, you must have a supported FPGA board connected to your MATLAB host computer using a supported connection type, and a supported synthesis tool.

Supported Xilinx FPGA Boards

This support package enables FIL simulation, FPGA data capture, and MATLAB AXI master for the boards in the table.

FPGA data capture and MATLAB AXI master are supported for Xilinx® devices using Vivado® projects. Xilinx ISE projects are not supported.

Device FamilyBoardEthernetJTAG PCI ExpressComments
FILFPGA Data CaptureMATLAB AXI MasterFILFPGA Data CaptureMATLAB AXI MasterFIL[a]FPGA Data CaptureMATLAB AXI Master

Xilinx Artix®-7

Digilent® Nexys™4 Artix-7

x  xxx    
Digilent Arty Boardxxxxxx    

Xilinx Kintex®-7

Kintex-7 KC705xxxxxxx   

Xilinx Kintex UltraScale™

Kintex UltraScale FPGA KCU105 Evaluation Kit

xxxxxx    

Xilinx Kintex UltraScale+™

Kintex UltraScale+ FPGA KCU116 Evaluation Kit

 xxxxx  xFor more information, see PCI Express MATLAB AXI Master.

Xilinx Spartan®-6

Spartan-6 SP605xxx       
Spartan-6 SP601xxx       
XUP Atlys Spartan-6xxx       

Xilinx Spartan-7

Digilent Arty S7-25   xxx    

Xilinx Virtex® UltraScale

Virtex UltraScale FPGA VCU108 Evaluation Kit

xxxxxx    

Xilinx Virtex UltraScale+

Virtex UltraScale+ FPGA VCU118 Evaluation Kit

 xxxxxx   

Xilinx Virtex-7

Virtex-7 VC707xxxxxxx   
Virtex-7 VC709   xxxx   

Xilinx Virtex-6

Virtex-6 ML605xxx       

Xilinx Virtex-5

Virtex ML505xxx       
Virtex ML506xxx       
Virtex ML507xxx       
Virtex XUPV5–LX110Txxx       

Xilinx Virtex-4

Virtex ML401xxx      

Note

Support for Virtex-4 device family will be removed in a future release.

Virtex ML402xxx      
Virtex ML403xxx      

Xilinx Zynq®

Zynq-7000 ZC702

   xxx    
Zynq-7000 ZC706   xxxx    
ZedBoard™  xxxx   Use the USB port marked "PROG" for programming.

ZYBO™ Zynq-7000 Development Board

   xxx    
PicoZed™ SDR Development Kit   xxx    
MiniZed™    xx   Supported only for FPGA data capture and MATLAB AXI master via FTDI JTAG.

Xilinx Zynq UltraScale+

Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

   xxx    

Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit

   xxx    

Zynq UltraScale+ MPSoC ZCU106 Evaluation Kit

   xxx    

Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

   xxx    

Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit

   xxx    

[a] FIL over PCI Express® connection is supported only for 64-bit Windows® operating systems.

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