Use this support package with these recommended versions:
Xilinx® Vivado® 2020.1
Xilinx ISE 14.7
Xilinx ISE is not supported for FPGA data capture or MATLAB® AXI master.
Xilinx ISE is required for FPGA boards in the Spartan®-6, Virtex®-4, Virtex-5, and Virtex-6 families.
For tool setup instructions, see Set Up FPGA Design Software Tools.
You can run FPGA-in-the-loop, FPGA data capture, or MATLAB AXI master over a JTAG cable to your board. However, each feature requires exclusive use of the JTAG cable, so you cannot run more than one feature at the same time. To allow other tools access to the JTAG cable, such as programming the FPGA, and Xilinx ChipScope, you must discontinue the JTAG connection in MATLAB. To release the JTAG cable:
FPGA-in-the-loop — Close the Simulink® model, or call the
release method of the System object™.
FPGA data capture — Close the FPGA Data Capture tool, release the System object, or close the Simulink model.
MATLAB AXI master — Call the
release method of the object.
For Xilinx boards, the JTAG clock frequency is 33 or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.
|Required Hardware||Required Software|
Digilent® download cable.
FTDI USB-JTAG cable
Install these D2XX drivers.
For the installation guide, see D2XX Drivers from the FTDI Chip website.
When simulating your FPGA design through Digilent JTAG cable with Simulink or MATLAB, you cannot use any debugging software that requires access to the JTAG; for example, Vivado Logic Analyzer.
You can run FPGA-in-the-loop, FPGA data capture, or MATLAB AXI master over an Ethernet connection. To use FPGA data capture and MATLAB AXI master over an Ethernet connection in a single HDL project, connect the FPGA data capture and MATLAB AXI master IPs to the same Ethernet MAC Hub IP using different port addresses.
|Required Hardware||Supported Interfaces||Required Software|
There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.
FPGA data capture and MATLAB AXI master support GMII, MII, and SGMII interfaces only.
RMII is supported with Vivado versions older than 2019.2.
Ethernet connection to Virtex-7 VC707 not supported for Vivado versions older than 2013.4.
FPGA-in-the-loop over a PCI Express® connection is supported only for 64-bit Windows operating systems.
MATLAB AXI master is supported over PCI Express for Xilinx Kintex® UltraScale+™ FPGA KCU116 Evaluation Kit boards.
||Vivado 2017.4 or newer.|