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MATLAB AXI Master Simulation

Prior to deploying your algorithm on an FPGA, you can simulate the algorithm and perform read and write operations to simulated memory or memory-mapped registers on your board. Use the provided SystemVerilog readmemory and writememory tasks to read and write memory-mapped locations on the board. Simulation is available for only the Vivado® Simulator, on which you can perform only behavior simulations.

To integrate the AXI master IP in your design, see Integrate MATLAB AXI Master IP in FPGA Design. After you integrate the AXI master IP in your design, create a SystemVerilog wrapper that includes your design under test (DUT), memory interface generator (MIG), AXI master IP, clock, and reset logic. You can then instantiate the wrapper in a SystemVerilog test bench and simulate.

HDL Wrapper Creation

Create a wrapper for the FPGA design. The wrapper includes all of the user logic and FPGA logic. The interface to the wrapper includes clock and reset ports and an optional DDR3 interface to the memory or other on-board peripherals. After creating and configuring the design in Vivado, navigate to the Sources window in Vivado. In the Sources tab, under Design Sources, right-click the design name and select Create HDL Wrapper. This action creates an HDL file named design_name_wrapper.v in the design_name/hdl folder, where design_name is the name of the Vivado project.

SystemVerilog Test Bench

HDL Verifier™ provides SystemVerilog tasks to interact with the design in a SystemVerilog simulation. After you create a SystemVerilog wrapper, instantiate the wrapper in a SystemVerilog test bench. The test bench also includes on-board IP models, such as memory models. Drive a clock and a reset signal to your DUT. To include definitions specific to HDL Verifier, import the hdlverifier package to the test bench by entering this code in the test bench file.

import hdlverifier::*;

To write data to memory locations or to read data from memory locations, use the writememory and readmemory SystemVerilog tasks, respectively, as detailed in the next two sections. For an example that uses AXI master simulation, see Access FPGA Memory Using JTAG-Based MATLAB AXI Master.

writememory(addr,wdata,burst_type) SystemVerilog Task

Write data to AXI4 memory-mapped slaves in simulation.

  • addr – Start address for write operation

    The address is zero-extended to 32 or 64 bits, depending on the AXI master IP address width. The address must refer to an AXI slave memory location controlled by the AXI master IP on your FPGA board. For more information, see Memory Mapping Guidelines.

  • wdata – Data words to write

    By default, the test bench writes data to a contiguous address block, incrementing the address for each operation. To turn off address increment mode and write each data value to the same location, set the burst_type parameter to HDLV_AXI_BURST_TYPE_FIXED.

  • burst_type – AXI4 burst type

    Specify HDLV_AXI_BURST_TYPE_INCR for increment mode, or HDLV_AXI_BURST_TYPE_FIXED for fixed-burst mode.

    In HDLV_AXI_BURST_TYPE_INCR mode, the AXI master reads a vector of data from contiguous memory locations, starting with the specified address. In HDLV_AXI_BURST_TYPE_FIXED mode, the AXI master reads all of the data from the same address.

readmemory(addr,length,burst_type) SystemVerilog Task

Read data out of AXI4 memory-mapped slaves in simulation.

  • addr – Start address for read operation

    The address is zero-extended to 32 or 64 bits, depending on the AXI master IP address width. By default, the address width is set to 32 bits. To set the width to 64 bits, specify parameter AXI_ADDR_WIDTH=64 in the HDL test bench. The address must refer to an AXI slave memory location controlled by the AXI master IP on your FPGA board. For more information, see Memory Mapping Guidelines.

  • length – Number of locations to read

    Specify the number of memory locations to read. By default, the test bench reads from a contiguous address block, incrementing the address for each operation. To turn off address increment mode and read repeatedly from the same location, set the burst_type parameter to HDLV_AXI_BURST_TYPE_FIXED.

  • burst_type – AXI4 burst type

    Specify HDLV_AXI_BURST_TYPE_INCR for increment mode, or HDLV_AXI_BURST_TYPE_FIXED for fixed-burst mode.

    In HDLV_AXI_BURST_TYPE_INCR mode, the AXI master reads a vector of data from contiguous memory locations, starting with the specified address. In HDLV_AXI_BURST_TYPE_FIXED mode, the AXI master reads all of the data from the same address.

Memory Mapping Guidelines

  • If the AXI master IP data width is 32 bits, the memory is 4 bytes aligned, and addresses have 4-byte increments (0x0, 0x4, 0x8). In this case, 0x1 is an invalid address and you get an error.

  • If the AXI master IP data width is 64 bits, the memory is 8 bytes aligned, and addresses have 8-byte increments (0x0, 0x8, 0x10). In this case, 0x1 or 0x4 are invalid addresses and will emit an error.

  • If the AXI master IP data width is 32 bits and the Burst type parameter is set to Increment, the address is incremented by 4 bytes.

  • If the AXI master IP data width is 64 bits and the Burst type parameter is set to Increment, the address is incremented by 8 bytes.

  • Do not use a 64-bit AXI master for accessing 32-bit registers.

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