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MATLAB AXI Master

Access AXI slave memory on FPGA board from MATLAB® or Simulink®

Access on-board memory locations from MATLAB or Simulink by using the MATLAB AXI master IP in your FPGA design. This IP connects to slave memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express, or Ethernet cable.

Functions

setupAXIMasterForVivado Add AXI master IP path to Vivado project
readmemoryRead data out of AXI4 memory-mapped slaves
writememoryWrite data to AXI4 memory-mapped slaves
releaseRelease JTAG or Ethernet cable resource
copyImageToHostSDCardPathCopy board-specific SD card image files to host SD card location
loadImageToTargetSDCardPathLoad board-specific SD card image files to target SoC device SD card location
loadBitstreamLoad custom FPGA bitstream and its corresponding DTB file to target SoC device

Objects

aximasterRead and write memory locations on FPGA board from MATLAB

Blocks

AXI Master ReadRead memory locations on FPGA board from Simulink
AXI Master WriteWrite memory locations on FPGA board from Simulink

Topics

Set Up MATLAB AXI Master

High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink.

Ethernet MATLAB AXI Master

Integrate and configure Ethernet MATLAB AXI master.

Ethernet MATLAB AXI Master for Xilinx Zynq SoC Devices

Configure Ethernet MATLAB AXI master for Xilinx Zynq SoC devices.

PCI Express MATLAB AXI Master

Integrate and configure MATLAB as AXI Master IP over PCI Express.

Use Simulink to Access FPGA Locations

Access memory-mapped locations on an FPGA board from Simulink.

MATLAB AXI Master Simulation

Simulate MATLAB AXI master using the Vivado simulator.

Featured Examples