The Frame Buffer with High-Definition Multimedia Interface (HDMI) template creates a Simulink® project with models to simulate and generate a video application with external memory frame buffer. This template forms the base for the Histogram Equalization Using Video Frame Buffer example. Use this template to simulate the full reference design of a video processing application on an FPGA with HDMI I/O and connection to an external memory frame buffer for advanced image processing designs.
Vision HDL Toolbox™
Computer Vision Toolbox™
SoC Blockset™ Support Package for Xilinx® Devices
HDMI video streams video data from an HDMI Rx block into the FPGA. The
FPGA implements a color-space transformation and your image processing algorithm. The
processed images then undergo the inverse color-space transformation and stream to the
HDMI Tx block. The FPGA algorithm is connected to the external memory
frame buffer Memory Channel
block configured in
AXI4-Stream Video Frame Buffer mode.
Due to hardware implementation, HDMI output requires an additional frame buffer for synchronization of the video stream data between clock domains and introduces an additional memory consumer in the overall system. You can model this system by using Memory Traffic Generator blocks to simulate the additional memory consumption. To model read and write transactions, use two Memory Traffic Generator blocks: one for read transactions and one for write transactions. The HDMI Output Buffer Write Traffic block models write transactions, and the HDMI Output Buffer Read Traffic block models read transactions.
The FPGA pixel model uses Video Stream Connector blocks to connect different subsystems and to connect to HDMI I/O blocks. This is required to be able to generate each subsystem as a separate IP in the implemented reference design from the model. Since the FPGA frame model is for simulation purposes only and is not used for implementation, the Video Stream Connector blocks are not modeled.
In MATLAB®, on the Project Shortcuts tab, click Open
FPGA pixel model. Double-click to open the
FPGA Algorithm, highlighted in green, contains feedthrough ports
Modify the content of the
FPGA Algorithm subsystem to incorporate
your desired vision processing algorithm, with complete simulation and code generation
of the surrounding video memory system. The pixelToFrameBuf and
pixelFromFrameBuf ports provide access to the external memory
Frame Buffer. For pure algorithm design and investigation,
in the Project Shortcuts tab, click Open FPGA frame
model, and repeat this step.