Templates and Guidelines

Guidelines and templates for SoC application models

Create a model for an SoC application by using an existing template or following the SoC model guidelines. SoC Blockset™ model templates in Simulink^® provide design patterns and implement best practices for creating an SoC application model. The suggested workflow shows the process to combine hardware user logic, software algorithms, a memory system, and I/O devices to create an SoC application model.

Topics

SoC Blockset Model Structure

Top level structure of SoC model.

Use Template to Create SoC Model

Create SoC models using Simulink Project templates.

Stream from FPGA to Processor Template
Stream from Processor to FPGA Template
SDR Template
HDMI Template
Frame Buffer with HDMI Template
RFSoC Template

Create an SoC Project Application

Step by step instructions and guidelines to create a SoC Blockset project and models for an SoC application.

STEP 1: Project and Top-Level Model
STEP 2: Software and Task Management on Processor
STEP 3: User Logic on FPGA
STEP 4: Memory and Register Channel Connections
STEP 5: Simulation and Analysis

Considerations for Multiple IPs in FPGA Model

When your FPGA model includes more than one block for which you'd like to generate HDL using HDL Coder™, you must use a connector model to connect your blocks.

Custom Hardware Board Configuration

Develop an SoC application model with a custom board configuration.

Troubleshooting

Build Error for Rapid Accelerator Mode

Unsupported simulation mode in SoC Blockset models and projects.

Featured Examples

Streaming Data from Hardware to Software

Presents a systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC Blockset. Applications are often partitioned between hardware logic and embedded processor on a system-on-chip (SoC) device to meet throughput, latency and processing requirements. You will design and simulate the entire application comprising of FPGA & processor algorithms, memory interface and task scheduling to meet the system requirements. You will then validate the design on hardware by generating code from the model and implementing on a SoC device.

Open Example

Random Access of External Memory

Model external memory accesses from FPGA for rotating an ASCII art image. Many applications require FPGA to access memory in random fashion as per the requirements of algorithm. You will learn how to design memory address generation along with other AXI4 master signals to read and write specific regions of memory using SoC Blockset. You will simulate, implement and verify your design on hardware.

Open Example

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Open Example

Histogram Equalization Using Video Frame Buffer

Video processing applications often store a full frame of video data to process the frame and modify the next frame. In such designs video frames are stored in external memory while FPGA resources are used to process same data. This example shows how to design a video application with HDMI input and output performing histogram equalization using external memory for video frame buffering.

Open Example

Hardware-Software Partitioning of a Motor Control Algorithm

Model a motor controller for SoC devices by partitioning the control and calibration algorithms between the FPGA and processor of the SoC.

Open Script

SoC Blockset Documentation

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