SoC Blockset™ exports reference designs for ASICs, FPGAs, and systems on a chip (SoC) by using Xilinx® and Intel® design tools. Automatically generate hardware and software code, and execute on an SoC device by using the SoC Builder tool. Code generation requires HDL Coder™, Embedded Coder®, or both.
|SoC Builder||Build, load, and execute SoC model on SoC, FPGA, and MCU boards|
|Memory Mapper||Configure memory map for SoC application|
|Task Mapping||Map tasks in the SoC to interrupt service routines on the hardware board|
|Peripheral Configuration||Map peripherals in the SoC model to peripheral registers in the MCU|
|Export custom reference design for HDL Workflow Advisor|
Choose between the SoC Builder tool and the
exportReferenceDesign function for deploying your design on
an SoC device.
Generate an SoC design and run it on an SoC device using the SoC Builder tool.
socExportReferenceDesign function to export a custom
reference design from an SoC Blockset model.
Mapping between tasks in an SoC application model and threads in generated code.
Version support for third-party tools.
Unsupported mode in when generating SoC design using SoC Builder.