While Iterator Subsystem
Repeat subsystem execution during simulation time step while logical expression is true
Libraries:
Simulink /
Ports & Subsystems
Description
The While Iterator Subsystem block is a Subsystem block preconfigured as a starting point for creating a subsystem
that repeats execution during a simulation time step while a logical condition is
true
. Execution is controlled by a While Iterator block inside the
subsystem. For an example, see ex_while_iterator_block
.
Use While Iterator Subsystem blocks to model:
Block diagram equivalent of a program
while
ordo-while
loop.An iterative algorithm that converges on a more accurate solution after multiple iterations.
When using simplified initialization mode, if you place a block that needs elapsed time (such as a Discrete-Time Integrator block) in a While Iterator Subsystem block, Simulink® displays an error.
If the output signal from a While Iterator Subsystem block is a function-call signal, Simulink displays an error when you simulate the model or update the diagram.
Ports
Input
Output
Block Characteristics
Extended Capabilities
Version History
Introduced before R2006a