Saturate on integer overflow — Method of overflow action off (default) | on
Select to have integer overflows saturate. Otherwise, overflows
wrap.
When you select this check box, saturation applies to every internal
operation on the block, not just the output, or result. In general, the code
generation process can detect when overflow is not possible. In this case,
the code generator does not produce saturation code.
For signed-integer data types, the unary minus of the most negative value
is not representable by the data type. In this case, the Saturate
on integer overflow check box controls the behavior of the
block:
Parameter Setting
Block Behavior
Examples
Saturate on integer overflow =
on
Values saturate to the most positive value of the integer
data type
For 8-bit signed integers, -128 maps to
127.
For 16-bit signed integers, -32768 maps to
32767.
For 32-bit signed integers, -2147483648 maps
to 2147483647.
Saturate on integer overflow =
off
Values wrap to the most negative value of the integer
data type
For 8-bit signed integers, -128 remains
-128.
For 16-bit signed integers, -32768 remains
-32768.
For 32-bit signed integers, -2147483648
remains -2147483648.
Programmatic Use
Block Parameter:SaturateOnIntegerOverflow
Type: character vector
Values:'off' | 'on'
Default:'off'
Sample time — Specify sample time as a value other than -1 -1 (default) | scalar | vector
Specify the sample time as a value other than -1. For more information, see Specify Sample Time.
double | fixed point[a] | half | integer[a] | single
Direct Feedthrough
yes
Multidimensional Signals
yes
Variable-Size Signals
no
Zero-Crossing Detection
no
[a]This block only supports signed fixed-point data types.
Extended Capabilities
C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.
HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL
implementation and synthesized logic.
HDL Architecture
This block has a single, default HDL architecture.
HDL Block Properties
ConstrainedOutputPipeline
Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline
Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see InputPipeline (HDL Coder).
OutputPipeline
Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see OutputPipeline (HDL Coder).
Complex Data Support
This block supports code generation for complex signals.
PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.
Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.
This block only supports signed fixed-point data types.
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