PCIe-5 Compliance Kit

R2026b
Open Live Script

Test the compliance of simulation models and channel topologies to the PCI Express gen 5 (PCIe-5) Base specification.

This PCIe compliance signal integrity kit includes all the Transfer nets, topologies, generic buffer models and compliance rules for a PCIe-5 high-speed SerDes interface. This includes PCIe-5 technology IBIS-AMI models for the SerDes transmitter and receiver, PCIe-5 compliance masks and transfer nets preconfigured for TX and RX characterization that are customizable for a PCIe-5 embedded channel.

This kit enables you to insert a channel design and characterize and validate its performance using the specification masks to determine if the channel has a high confidence of success. If the channel does not meet the compliance masks or BER targets, further investigation or redesign, along with simulation, will need to be performed to determine possible changes to meet compliance.

Open PCIe-5 Kit

Open the PCIe-5 kit in the Serial Link Designer app using the openSignalIntegrityKit helper function.

openSignalIntegrityKit("PCIe_Gen5_NVMe");

PCIe_Gen5_NVMe.PNG

Kit Overview

  • Project Name: PCIe_Gen5_NVMe

  • Interface Name: PCIe_Gen5

  • Target Signaling Rate: 32.0 GT/s; (Nyquist frequency: 16.0 GHz, UI = 31.25 ps)

The PCIe-5 kit defines five schematic sets:

  • All_Sheets: All schematic sheets

    • Cal_Channel_Ref_Design_32Gbps: Base Specification Reference Design for 32 GT/s

  • Channel_Tolerancing: Calibration Channel Stressed RX Testing

  • Compliance_Board_Testing: Network Characteristics for Calibration Channel Models and Reference Design Models

  • Tx_and_Rx_Pkg_Tests: Testing of Tx and Rx Characteristics and Package Model

For more information about the PCIe-5 channel compliance schematics, transfer net properties and compliance rules, refer to the document PCIe_Gen5.pdf located inside the kit project directory.

References

  • PCI‑SIG, PCI Express Base Specification Revision 5.0, PCI‑SIG, Inc.

  • PCI‑SIG, PCI Express Card Electromechanical Specification Revision 5.0, PCI‑SIG, Inc.

See Also