Results of Pre-Layout Analysis in Serial Link
The Serial Link Designer app produces one or more reports and logs for each simulation and process you run.
The tabs within a report are organized to aid in the process of progressive discovery. The first tab is the log tab, providing a progress summary of the analysis and its errors and warnings. The other tabs contain summaries of the data and successively more detailed information, letting you track down a particular result to a specific simulation file and transition number or time.
Validation reports indicate the syntax errors in the data. When relevant, the reports provide the corresponding part name, IBIS file and component names, and timing file and model names.
|Validation Summary||Number and location of warnings and errors.|
Parts or pins in parts that are not referenced in the transfer netlist or timing model.
|Transfer Net Summary|
Details on each transfer net such as whether the type of the net is data, clock, or strobe, whether the net is differential or single-ended, and the number of nodes. This report also lists information on the clock, noise, and probe points.
Details on each part.
Details on every signal integrity, HSPICE, and IBIS parameter or extension associated with each model in the design. This includes model name, corner and mode information, waveform DRC and timing extensions among other parameters.
|Part Pin Summary|
Summary of part Transfer Nets and timing pin definitions.
|Differential Pin Summary|
Lists of the differential pins and components associated with each part.
|Timing Delay Summary|
Summary of all output delays and setup and hold statements in each timing model.
Lists of most of the waveform DRC rules and timing levels used by the product. The report includes the actual parameter used (following the precedence rules) and the value assigned to that parameter.
|Transfer Net Errors|
Inconsistencies between Transfer Nets, IBIS components and timing models. The part, IBIS and timing files listed are not necessarily where the error occurred, but simply a listing of all files involved in the error checking.
Netlist Generation Report
The Netlist Generation Report contains multiple tabs of data that summarize the netlists that were generated for analysis.
Information related to generating simulation decks such as simulation modes, filter sensitivities, clock recovery information, and more.
Detailed information of all the signal integrity parameters such as jitter, noise, frequency, clock recovery, BER, and more.
Channel Analysis Report
The Channel Analysis Report provides a summary of the simulations that has been run. Tabs for network characterization, statistical analysis, time domain analysis, and the worst case PDA (peak distortion analysis) bit pattern are provided.
|Channel Analysis Summary|
Status of channel analysis, error and warning messages.
|Network||Network characterization results which includes unequilized system responses such as impulse response, step response, pulse response, S-parameters, transfer functions, and more.|
|Statistical||Statistical analysis results such as statistical eye, BER, bathtub, contour, crosstalk, and more.|
|Time Domain||Time domain analysis results such as statistical eye, BER, bathtub, contour, deterministic jitter probability function, crosstalk, and more.|
The data pattern which produces the minimum eye opening at the center of the eye.
Serial Link Designer | Signal Integrity Viewer