Clock Delay Through Buffers and PLLs

The Parallel Link Designer app combines the etch delays of relevant nets with the delay across the buffer or PLL to find the overall path delay.

Clock Delay Through Clock Buffer

The Parallel Link Designer app simulates the input and output nets of the clock buffer. It then combines the etch delays with the delay across the clock buffer to determine the delay of the overall path. When multiple analysis corners are enabled, the app evaluates each corner case and uses the overall min/max values for timing analysis.

$$\begin{array}{c}{R}_{\min }=R_{\min }\_IC+\\ \min \{[\min \_NX+R_{\min }\_OC](\text{Corner 1})\\ [\min \_NX+R_{\min }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\min \_NX+R_{\min }\_OC](\text{Corner N)}}\end{array}$$

$$\begin{array}{c}{R}_{\max }=R_{\max }\_IC+\\ \max \{[\max \_NX+R_{\max }\_OC](\text{Corner 1})\\ [\max \_NX+R_{\max }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\max \_NX+R_{\max }\_OC](\text{Corner N)}}\end{array}$$

$$\begin{array}{c}{F}_{\min }=F_{\min }\_IC+\\ \min \{[\min \_NX+F_{\min }\_OC](\text{Corner 1})\\ [\min \_NX+F_{\min }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\min \_NX+F_{\min }\_OC](\text{Corner N)}}\end{array}$$

$$\begin{array}{c}{F}_{\max }=F_{\max }\_IC+\\ \max \{[\max \_NX+F_{\max }\_OC](\text{Corner 1})\\ [\max \_NX+F_{\max }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\max \_NX+F_{\max }\_OC](\text{Corner N)}}\end{array}$$

Here, IC refers to etch delay of the clock input to buffer, OC refers to etch delay of the clock output from the buffer, and NX refers to buffer input to output delay.

Clock Buffer Timing Model Example

Consider a device containing two independent clock buffers, each with five outputs: The delay from input to output ranges from 500ps to 2.5ns, with outputs always firing within 400ps (± 200ps) of each other. The OA[5:1] outputs provide a non-inverted copy of the CKINA input, while the OB[5:1] outputs provide an inverted copy of the CKINB input. The timing model is:

MODEL: clock_buff
DESCRIPTION: Example Clock Buffer Timing Model
SOURCE: SiSoft
PINDEF: 20 PINS
INPUTS
CKINA = INA
CKINB = INB
OUTPUTS
CKOUTA = OA[5:1]
CKOUTB = OB[5:1]
BIDIR
UNINTERESTING
OE = OEA OEB
MON = MON
END_PINDEF
CLOCK_SKEW R CKOUTA *TO CKOUTA -0.200 0.200
CLOCK_SKEW F CKOUTA *TO CKOUTA -0.200 0.200
CLOCK_SKEW R CKOUTB *TO CKOUTB -0.200 0.200
CLOCK_SKEW F CKOUTB *TO CKOUTB -0.200 0.200
DELAY NX CKINA *TO CKOUTA 0.500 2.500
DELAY IX CKINB *TO CKOUTB 0.500 2.500
END_MODEL

Clock Delay Through PLL

The Parallel Link Designer app simulates the input, output, and feedback nets of the PLL. It then combines the etch delays with the delay across the PLL to determine the delay of the overall path. When multiple analysis corners are enabled, the app evaluates each corner case and uses the overall min/max values for timing analysis.

$$\begin{array}{c}{R}_{\min }=R_{\min }\_IC+\\ \min \{[\min \_NX-R_{\max }\_FB+R_{\min }\_OC](\text{Corner 1})\\ [\min \_NX-R_{\max }\_FB+R_{\min }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\min \_NX-R_{\max }\_FB+R_{\min }\_OC](\text{Corner N)}}\end{array}$$

$$\begin{array}{c}{R}_{\max }=R_{\max }\_IC+\\ \max \{[\max \_NX-R_{\min }\_FB+R_{\max }\_OC](\text{Corner 1})\\ [\max \_NX-R_{\min }\_FB+R_{\max }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\max \_NX-R_{\min }\_FB+R_{\max }\_OC](\text{Corner N)}}\end{array}$$

$$\begin{array}{c}{F}_{\min }=F_{\min }\_IC+\\ \min \{[\min \_NX-R_{\max }\_FB+F_{\min }\_OC](\text{Corner 1})\\ [\min \_NX-R_{\max }\_FB+F_{\min }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\min \_NX-R_{\max }\_FB+F_{\min }\_OC](\text{Corner N)}}\end{array}$$

$$\begin{array}{c}{F}_{\max }=F_{\max }\_IC+\\ \max \{[\max \_NX-R_{\min }\_FB+F_{\max }\_OC](\text{Corner 1})\\ [\max \_NX-R_{\min }\_FB+F_{\max }\_OC](\text{Corner 2})\\ \mathrm{...}\\ [\max \_NX-R_{\min }\_FB+F_{\max }\_OC](\text{Corner N)}}\end{array}$$

Here, IC refers to etch delay of the clock input to buffer, OC refers to etch delay of the clock output from the buffer, FB refers to feedback path delay, and NX refers to buffer input to output delay.

PLL Timing Model Example

Consider a device containing a single PLL with 10 outputs: The effective delay (including the feedback loop) of the device ranges from -110ps to 150ps, with outputs always firing within 80ps (± 40ps) of each other. The timing model is:

MODEL: pll
DESCRIPTION: Example PLL Timing model
SOURCE: SiSoft
PINDEF: 31 PINS
INPUTS
CKIN = CKIN
FBIN = FBIN
OUTPUTS
FBOUT = FBOUT
CKOUT = Y[9:0]
BIDIR
UNINTERESTING
OE = OE
OS = OS
END_PINDEF
CLOCK_SKEW R CKOUT *TO CKOUT -0.040 0.040
CLOCK_SKEW F CKOUT *TO CKOUT -0.040 0.040
DELAY NX CKIN *TO CKOUT -0.110 0.150
DELAY PLL FBIN *TO FBOUT
END_MODEL

Related Topics

• Timing Analysis
• Clock Skew in Synchronous Interface Timing
• Clock Skew in Source-Synchronous Interface Timing
• Timing Analysis Reports