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ADD

  • Library:
  • ADD block

Description

The ADD block implements the ADD ladder logic instruction. When the rung conditions are true, the block adds source A (srcA) to source B (srcB) and outputs the result to the destination (dest).

Ports

Input

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Controls the execution of the block. EnableIn reflects the rung state preceding the block. If the rung state preceding the block is false, EnableIn is false, the block does not execute and the outputs are not updated.

The first input signal to the addition operation.

Data Types: int8 | int16 | int32 | single

The second input signal to the addition operation.

Data Types: int8 | int16 | int32 | single

Output

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By default, EnableOut follows the state of EnableIn. If the EnableIn input to the block is false, the logic implemented by the block is not executed and EnableOut signal is set to false.

Output signal resulting from the addition operation.

Data Types: int8 | int16 | int32 | single

See Also

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Introduced in R2019a