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Frequency Division Using Single Modulus Prescaler

Open Script

Open the model singleModulusPrescaler. The model consists of a Pulse Generator and a Single Modulus Prescaler block.

model='singleModulusPrescaler';
open_system(model)

The period of the incoming pulse at the clk in port is 4e-7 s. So, the incoming signal has a frequency of 2.5 MHz. The div-by value is set at 2.

Run the simulation for 2e-6 s. The frequency of the output signal is 1.25 MHz.

sim(model);