Generate HDL and HLS Code from a Fixed-Point Viterbi Decoder

R2026b

This example shows how to generate HDL and HLS code from a MATLAB® function that implements a rate 1/2, constraint-length 7 Viterbi decoder using fixed-point arithmetic.

Viterbi decoders are widely used in digital communication systems to decode convolutional codes. They find the most likely transmitted sequence by searching through a trellis of possible state transitions. Because this design already uses fixed-point data types (fi, numerictype, fimath) and bit-level operations (bitget, bitsliceget, bitconcat), it does not require floating-point to fixed-point conversion before code generation.

Note

This example requires Communications Toolbox™.

Examine the MATLAB Design and Test Bench

Set up the MATLAB function and test bench for this example. In the MATLAB Command Window, enter:

mlhdlc_demo_setup("mlhdlc_viterbi");
This command opens a temporary working folder with the files required to run this example. The folder includes these files:

  • MATLAB function

  • Test bench

  • <model>_runme.m script, which includes the commands to generate HDL code

  • <model>_runme_hls.m script, which includes the commands to generate HLS code

The MATLAB function, mlhdlc_viterbi, accepts a 2-element vector of 3-bit unsigned fixed-point soft-decision symbols and returns a decoded Boolean bit. The function implements three processing stages: a branch metric unit (BMU), an add-compare-select (ACS) unit with 64 states, and a traceback unit (TBU) with a depth of 32.

To view the function, enter:

open mlhdlc_viterbi.m;

The test bench file, mlhdlc_viterbi_tb, generates random input bits, encodes them with a convolutional encoder, passes the encoded symbols through the Viterbi decoder, and reports the bit error rate (BER). To view the test bench, enter:

open mlhdlc_viterbi_tb.m;

Simulate the Design

To check for run-time errors, simulate the design by running the test bench. In the MATLAB Command Window, enter:

mlhdlc_viterbi_tb;

Generate HDL Code

The mlhdlc_viterbi_runme script specifies the target files, enables the settings required for this example, and generates HDL code.

The script specifies the MATLAB function and test bench, then creates an HDL configuration object by using the coder.config function. It associates the test bench with the configuration object.

designName = "mlhdlc_viterbi";
designTB = "mlhdlc_viterbi_tb";
cfg = coder.config("hdl");
cfg.TestBenchName = designTB;

The script specifies the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vivado";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

The script then generates code:

codegen("-config", "cfg", designName, "-launchreport");

Run the Script

First, modify the mlhdlc_viterbi_runme script. The script disables synthesis by default. Set the value for the SynthesizeGeneratedCode property to true:

cfg.SynthesizeGeneratedCode = true;

Update the settings for your synthesis tool:

cfg.SynthesisTool = "Xilinx Vivado";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

Then, generate code by running the script:

mlhdlc_viterbi_runme

After code generation completes, the report opens. Examine the generated HDL code in the report.

Generate HLS Code

The mlhdlc_viterbi_runme_hls script specifies the target files, enables the settings required for this example, and generates HLS code.

The script specifies the MATLAB function and test bench, then creates an HLS configuration object by using the coder.config function. It associates the test bench and enables simulation.

designName = "mlhdlc_viterbi";
designTB = "mlhdlc_viterbi_tb";
cfg = coder.config("hls");
cfg.TestBenchName = designTB;
cfg.GenerateHLSTestBench = true;
cfg.SimulateGeneratedCode = true;

The script specifies the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vitis HLS";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

The script then generates code:

codegen("-config", "cfg", designName, "-launchreport");

Run the Script

First, modify the mlhdlc_viterbi_runme_hls script. The script disables synthesis by default. Set the value for the SynthesizeGeneratedCode property to true:

cfg.SynthesizeGeneratedCode = true;

Depending on your synthesis tool, set one of these flags to true:

isCodingForStratusHLS = false;
isCodingForVitisHLS = true;

Depending on your synthesis tool, update these synthesis tool settings:

if isCodingForStratusHLS
    cfg.SynthesisTool = "Cadence Stratus HLS";
elseif isCodingForVitisHLS
    cfg.SynthesisTool = "Xilinx Vitis HLS";
    cfg.SynthesisToolChipFamily = "Artix7";
    cfg.SynthesisToolDeviceName = "xa7a100t";
    cfg.SynthesisToolPackageName = "csg324";
    cfg.SynthesisToolSpeedValue = "-1I";
end

Then, generate code by running the script:

mlhdlc_viterbi_runme_hls

After code generation completes, the report opens. Examine the generated HLS code in the report.

See Also

Functions

Topics