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DUT Port Configuration Parameters

These parameters reside in HDL Code Generation > Global Settings, in the Ports tab in the Configuration Parameters dialog box.

Use trigger signal as clock

This setting is a parameter in the HDL Code Generation > Global Settings > Ports tab in the Configuration Parameters dialog box.

Settings

Default: Off

On

For triggered subsystems, use the trigger input signal as a clock in the generated HDL code. Make sure that the Clock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.

Off

For triggered subsystems, do not use the trigger input signal as a clock in the generated HDL code.

Command-Line Information

Property: TriggerAsClock
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to generate HDL code that uses the trigger signal as clock for triggered subsystems within the sfir_fixed/symmetric_fir DUT subsystem, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl ('sfir_fixed/symmetric_sfir','TriggerAsClock','on')
  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','TriggerAsClock','on')
    makehdl('sfir_fixed/symmetric_fir')

Enable HDL DUT port generation for tunable parameters

Disable this setting to prevent creation of DUT input ports for tunable parameters in the generated HDL code.

Settings

Default: On

On

The code generator creates DUT input ports for the tunable parameters signals in the generated HDL code.

Off

The code generator preserves the tunable parameters and does not create DUT input ports in the generated HDL code. Selecting off might speed up code generation.

Command-Line Information

Property: GenDUTPortForTunableParam
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as tunable parameters for the sfir_fixed/symmetric_fir DUT subsystem, to generate DUT input ports in the HDL code, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl ('sfir_fixed/symmetric_sfir','GenDUTPortForTunableParam','on')
  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','GenDUTPortForTunableParam','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Generate DUT Ports for Tunable Parameters

Balance delays for generated DUT input ports

Enable this setting to insert matching delays on generated DUT inport port paths. Disable this setting to prevent HDL Coder™ from inserting matching delays on paths with stable inputs. Disable this setting if you do not intend to change the tunable parameter associated with the generated DUT input port while running your design on hardware. Preventing matching delays on stable paths in the DUT reduces the amount of resources needed for your design.

Settings

Default: On

On

HDL Coder inserts matching delays on the path of generated DUT input ports for tunable parameters signals in the generated HDL code.

Off

HDL Coder does not insert matching delays on the path of generated DUT input ports for tunable parameters signals in the generated HDL code.

Dependency

To disable this parameter, select the Enable HDL DUT input port generation for tunable parameters check box.

Command-Line Information

Property: BalanceDelaysForTunableParam
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as tunable parameters for the sfir_fixed/symmetric_fir DUT subsystem, to prevent matching delays on the generated DUT input port path in the HDL code, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_sfir',...
        'BalanceDelaysForTunableParam','off')
  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','BalanceDelaysForTunableParam','off')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Generate DUT Ports for Tunable Parameters

Enable HDL DUT port generation for test points

Enable this setting to create DUT output ports for the test point signals in the generated HDL code.

Settings

Default: Off

On

When you enable this setting, the code generator creates DUT output ports for the test point signals in the generated HDL code. You can observe the test point signals and debug your design by connecting a Scope block to the output ports corresponding to these signals.

Off

When you disable this setting, the code generator preserves the test point signals and does not create DUT output ports in the generated HDL code.

Note

When you designate test points for states inside a Stateflow® Chart, the code generator ignores this setting.

Command-Line Information

Property: EnableTestpoints
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as testpoints for the sfir_fixed/symmetric_fir DUT subsystem, to generate DUT output ports in the HDL code, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl ('sfir_fixed/symmetric_sfir','EnableTestpoints','on')
  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','EnableTestpoints','on')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Model and Debug Test Point Signals with HDL Coder

Balance delays for generated DUT output ports

Enable this setting to insert matching delays on generated DUT output port paths. Disable this setting to prevent HDL Coder from inserting matching delays on paths to output ports generated for test points. Preventing matching delays on test point output port paths in the DUT reduces the amount of resources needed for your design and reduces the latency of test points. Disable this property to probe hardware directly without added latency to the test point signal.

Note

Disabling this property affects the simulation behavior of test points in the original model.

Settings

Default: On

On

HDL Coder inserts matching delays on the path of DUT output ports generated for test point signals in the generated HDL code.

Off

HDL Coder does not insert matching delays on the path of DUT output ports generated for test point signals in the generated HDL code.

Dependency

To disable this parameter, select the Enable HDL DUT output port generation for test points check box.

Command-Line Information

Property: BalanceDelaysForTestpoints
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as testpoints for the sfir_fixed/symmetric_fir DUT subsystem, to prevent matching delays on the generated DUT output port path in the HDL code, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_sfir',...
        'BalanceDelaysForTestpoints','off')
  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','BalanceDelaysForTestpoints','off')
    makehdl('sfir_fixed/symmetric_fir')

See Also

Model and Debug Test Point Signals with HDL Coder

Scalarize ports

Flatten vector ports into a structure of scalar ports in VHDL® code.

Settings

Default: Off

On

When generating code for a vector port, generate a structure of scalar ports.

Off

When generating code for a vector port, generate a type definition and port declaration for the vector port.

dutlevel

When generating code for a vector port, generate a structure of scalar ports for vector ports that are at only DUT level. The DUT subsystem does not have to be at the top level of your model.

Dependency

When the target language (specified by the Language option) is VHDL, this option is enabled.

Command-Line Information

Property: ScalarizePorts
Type: character vector
Value: 'on' | 'off' | 'dutlevel'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

See Also

Scalarization of Vector Ports in Generated VHDL Code

Max number of I/O pins for FPGA deployment

Specify the maximum number of I/O pins for your target FPGA.

Settings

Default: 5000.

If the DUT pin count in the generated code exceeds the maximum number of I/O pins set by this parameter, HDL Coder generates a warning in the HDL Code Generation Check Report.

Command-Line Information

Property: IOThreshold
Type: int32
Value: positive integer
Default: 5000

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

See Also

coder.HdlConfig