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Improve Resource Sharing with Clone Detection and Replacement

This example shows how you can automatically identify and replace recurring patterns by using the Clone Detector App. Consequently, it also improves opportunities for optimizing the model by using resource sharing. The Clone Detector App refactors models by identifying clones in a design and replacing clones with links to subsystem blocks in a library. This example uses a model that has already been modified for optimal resource sharing by using the Clone Detector App. To learn more about these modifications, see "Improve Resource Sharing with Design Modifications."

Clone Detection

Clone Detection is a tool that can be used to identify modeling patterns in a design that are similar to a few sample patterns provided as inputs through a custom library file. Once the Clone Detector App identifies these patterns, it replaces the patterns with atomic subsystems. This enables the generation of optimal code through code reuse and results in better resource utilization through sharing of resources among the atomic subsystems. For more information regarding Clone Detection, please refer to Enable Component Reuse by Using Clone Detection (Simulink Check).

Set Up Model for Resource Sharing

This edited model is saved as hdlcoderParkTransformShare.slx. Copy this version of the model into the temporary directory using the following commands:

design_name = 'hdlcoderParkTransformShare';
design_new_name = 'hdlcoderParkTransformShareCopy';

hdlc_demo_dir = fullfile(matlabroot, 'toolbox', 'hdlcoder', 'hdlcoderdemos');
hdlc_temp_dir = [tempdir 'hdlcoderParkTransformDir'];

% Create a temporary folder and copy the Simulink model.
cd(tempdir);
[~, ~, ~] = rmdir(hdlc_temp_dir, 's');
mkdir(hdlc_temp_dir);
cd(hdlc_temp_dir);

copyfile(fullfile(hdlc_demo_dir, [design_name,'.slx']), fullfile(hdlc_temp_dir, [design_new_name,'.slx']), 'f');

% Open the model.
open_system(design_new_name);

Set a SharingFactor of 6 on the subsystem of interest and generate HDL along with the corresponding reports from the model.

subsystem = [design_new_name '/DUT'];
hdlset_param(subsystem, 'SharingFactor', 6);
makehdl(subsystem);
### Generating HDL for 'hdlcoderParkTransformShareCopy/DUT'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoderParkTransformShareCopy', { 'HDL Code Generation' } )">hdlcoderParkTransformShareCopy</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoderParkTransformShareCopy'.
### Begin compilation of the model 'hdlcoderParkTransformShareCopy'...
### Applying HDL optimizations on the model 'hdlcoderParkTransformShareCopy'...
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 39 cycles.
### Output port 2: 39 cycles.
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('gm_hdlcoderParkTransformShareCopy_vnl')">gm_hdlcoderParkTransformShareCopy_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoderParkTransformShareCopy'.
### MESSAGE: The design requires 6 times faster clock with respect to the base rate = 6.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_sincos_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_sincos_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_sub_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_sub_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_mul_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_mul_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_add_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_add_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_mul_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_mul_single_block.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_uminus_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_uminus_single.vhd.
### Working on DUT_tc as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT_tc.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT.vhd.
### Generating package file hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT_pkg.vhd.
### Code Generation for 'hdlcoderParkTransformShareCopy' completed.
### Generating HTML files for code generation report at <a href="matlab:web('/tmp/Bdoc21a_1606923_244180/hdlcoderParkTransformDir/hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/html/hdlcoderParkTransformShareCopy_codegen_rpt.html');">hdlcoderParkTransformShareCopy_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc21a_1606923_244180/hdlcoderParkTransformDir/hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT_report.html
### HDL check for 'hdlcoderParkTransformShareCopy' complete with 0 errors, 1 warnings, and 1 messages.
### HDL code generation complete.

The High-level Resource Report shows that the resource utilization for the design was estimated to be:

             Resource              Usage
     _________________________   ________
     Multipliers                 13
     Adders/Subtractors          178
     Registers                   1012
     Total 1-Bit Registers       16888
     RAMs                        0
     Multiplexers                610
     I/O Bits                    196
     Static Shift operators      8
     Dynamic Shift operators     8

You can also run synthesis workflow on the model. The synthesis results for this model are:

             Resource             Usage
     _________________________   ________
     Slice LUTs                  8792
     Slice Registers             8419
     DSPs                        13
     Block Ram Tile              0
     URAM                        0

For more details regarding synthesis workflow, see HDL Code Generation and FPGA Synthesis from Simulink Model.

Use Clone Detection to Optimize the Model for Resource Sharing

Before you use the Clone Detector App, create a customer library that contains each repeating pattern in the model as an Atomic Subsystem. For this example, you are given a custom library called hdlcoderParkTransformShareLib.slx.

% Copy the library into the temporary directory
lib_name = 'hdlcoderParkTransformShareLib';
lib_new_name = 'hdlcoderParkTransformShareLibCopy';

copyfile(fullfile(hdlc_demo_dir, [lib_name,'.slx']), fullfile(hdlc_temp_dir, [lib_new_name,'.slx']), 'f');

% Open the custom library
open_system('hdlcoderParkTransformShareLibCopy');

Replace patterns of the model with the library containing the Atomic Subsystem. To configure the Clone Detector App and replace the clones, refer to Enable Component Reuse by Using Clone Detection (Simulink Check). Specifically, follow the instructions in the Set the Parameters for Clone Detection section to link the library for clone detection, and set the Maximum number of different parameters value to 0.

Then, follow the Replace Clones section to apply this library to the model for exact clone replacement.

Notice that all the patterns in the original model has been replaced with atomic subsystems from the library as shown below:

Save the changes made to this system. In the Simulink Editor, on the Simulation tab, click Save.

Compare Results from Optimized Model

Since this model contains the Sin, Cos, and Product blocks inside atomic subsystems, they can now be shared and results in an improvement in resource utilization.

subsystem = [design_new_name '/DUT'];
hdlset_param(subsystem, 'SharingFactor', 3);
% Generate HDL code and the corresponding reports for the optimized model
makehdl(subsystem);
### Generating HDL for 'hdlcoderParkTransformShareCopy/DUT'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoderParkTransformShareCopy', { 'HDL Code Generation' } )">hdlcoderParkTransformShareCopy</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoderParkTransformShareCopy'.
### Begin compilation of the model 'hdlcoderParkTransformShareCopy'...
### Applying HDL optimizations on the model 'hdlcoderParkTransformShareCopy'...
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 33 cycles.
### Output port 2: 33 cycles.
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('gm_hdlcoderParkTransformShareCopy_vnl')">gm_hdlcoderParkTransformShareCopy_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoderParkTransformShareCopy'.
### MESSAGE: The design requires 3 times faster clock with respect to the base rate = 6.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_sincos_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_sincos_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_sub_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_sub_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_mul_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_mul_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_add_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_add_single.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT/nfp_uminus_single as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/nfp_uminus_single.vhd.
### Working on DUT_tc as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT_tc.vhd.
### Working on hdlcoderParkTransformShareCopy/DUT as hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT.vhd.
### Generating package file hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT_pkg.vhd.
### Code Generation for 'hdlcoderParkTransformShareCopy' completed.
### Generating HTML files for code generation report at <a href="matlab:web('/tmp/Bdoc21a_1606923_244180/hdlcoderParkTransformDir/hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/html/hdlcoderParkTransformShareCopy_codegen_rpt.html');">hdlcoderParkTransformShareCopy_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc21a_1606923_244180/hdlcoderParkTransformDir/hdl_prj/hdlsrc/hdlcoderParkTransformShareCopy/DUT_report.html
### HDL check for 'hdlcoderParkTransformShareCopy' complete with 0 errors, 1 warnings, and 1 messages.
### HDL code generation complete.

After sharing, the High-level Resource Report shows that the resource utilization for the design was estimated to be:

             Resource             Usage
     _________________________   ________
     Multipliers                 13
     Adders/Subtractors          177
     Registers                   1004
     Total 1-Bit Registers       16657
     RAMs                        0
     Multiplexers                610
     I/O Bits                    196
     Static Shift operators      8
     Dynamic Shift operators     8

Notice that the Adders/Subtractors, Registers, and Total 1-Bit Registers counts have reduced after the atomic subsystems are shared.

You can also run synthesis workflow on the model. The synthesis results for this model are:

             Resource             Usage
     _________________________   ________
     Slice LUTs                  8848
     Slice Registers             8308
     DSPs                        13
     Block Ram Tile              0
     URAM                        0

Notice that the Slice Registers count has reduced after sharing.