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Polyphase Channelizer

This example shows how to use the HDL-optimized Channelizer block to process incoming analog-to-digital converter (ADC) samples and produce a spectrum that has 512 MHz of bandwidth. MATLAB® displays the resulting spectrum plot by using FPGA API functions over a TCP/IP connection. The channelizer data sent back is in limited bursts, which are triggered by an AXI4 register in a capture loop. The model also contains an interface to the digital-to-analog converter (DAC) by using a numerically-controlled oscillator (NCO) to drive a tone commanded at some frequency over AXI4.


  • Vivado® Design Suite with a supported version listed in Supported EDA Tools and Hardware

  • Xilinx® Zynq® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit

  • HDL Coder™

  • HDL Coder Support Package for Xilinx FPGA and SoC Devices

Open Example

Open the example project and copy the example files to a temporary directory.

1. Navigate to the RFSoC root example directory of HDL Coder Support Package for Xilinx FPGA and SoC Devices by entering these commands at the MATLAB command prompt.

example_root = (hdlcoder_rfsoc_examples_root)
cd (example_root)

2. Copy all of the example files in the PolyphaseChannelizer folder to a temporary directory.

Simulate Channelizer Model

To understand the channelizer model in more detail, run the simulation of rfsocChannelizer.slx and view the power spectrum view and spectrogram.

You can see the channelizer processing inside this block: rfsocChannelizer/PolyphaseChannelizer/Channelizer Receive Processing. The FFT_Capture logic captures data based off of a trigger condition called TriggerCapture, which is driven by an AXI4 register. The state machine does not wait for a trigger and processes the next available frame from the channelizer to the direct memory access (DMA). The channelizer block Start-Of-Frame and Valid control lines are used to help determine when to latch onto the frame.

Generate HDL and Synthesize Bitstream

Right-click the channelizer subsystem device under test (DUT). Select HDL Code, then click HDL Workflow Advisor. In step 1.1 of the HDL Workflow Advisor, select Target platform as Xilinx Zynq Ultrascale+ RFSoC ZCU111 Evaluation Kit or Xilinx Zynq Ultrascale+ RFSoC ZCU216 Evaluation Kit.

Before proceeding to the next step, set these reference design parameters to the indicated values.

  • AXI4-Stream DMA data width to 64

  • ADC sampling rate (MHz) to 2048

  • ADC decimation mode (xN) to 4

  • ADC samples per clock cycle to 4

  • ADC mixer type to Bypassed

  • DAC sampling rate (MHz) to 2048

  • DAC interpolation mode (xN) to 4

  • DAC samples per clock cycle to 4

  • DAC mixer type to Bypassed

  • ADC/DAC NCO mixer LO (GHz) to Disabled

  • Enable multi-tile sync to false

If you are using a ZCU216 board, additionally set the DAC DUC mode parameter to Full DUC Nyquist (0-Fs/2).

After the bitstream is done compiling, program the FPGA bit file if you are using an HDL Workflow Advisor script.

Channelizer Spectrum Data Capture

The FPGA returns the output of the channelizer, which is frequency domain data of the spectrum. The capture logic fetches a frame upon receiving the signal condition over AXI4. With the board programmed, run the script hostIO_rfsocChannelizer_interface.m.

% %%Data capture loop
% for ii=1:150
%    writePort(hFPGA,"TriggerCapture",false);
%    writePort(hFPGA,"TriggerCapture",true);
%    writePort(hFPGA,"TriggerCapture",false);
%    rd_data = readPort(hFPGA,"S2MM_Data");
%    idx = mod(ii,length(FrequencyArr)) + 1;
%    nco_tone = FrequencyArr(idx);
%    fprintf('Changing NCO Tx tone to %d MHz \n',nco_tone);
%    writePort(hFPGA,"AXI4_NCO_incr",uint16(incrScale*nco_tone*1e6));
%    fft_frame = reinterp_stream_data(rd_data);
%    spectrum = 20*log10(abs(fft_frame(1:256)));
%    scopeSpectrum(spectrum);
%    scopeSpectrogram(spectrum);
% end
% disp('Done frequency sweep');

Spectrogram and spectrum plots are displayed for 150 captures. The NCO is commanded with different tones from an array that is declared before the capture.