Generate Board-Independent IP Core from MATLAB Algorithm
When you open the HDL Workflow Advisor and run the
IP Core Generation
workflow for your Simulink® model, you can specify a generic Xilinx® platform or a generic Intel® platform. The workflow then generates a generic IP core that you can integrate
into any target platform of your choice. For IP core
integration, define and register a custom reference design for your target board.
Requirements and Limitations for IP Core Generation
You cannot generate an HDL IP core without any AXI4 slave interface. At least one DUT port must map to an AXI4 or AXI4-Lite interface. To generate an HDL IP core without any AXI4 slave interfaces, use the Simulink IP core generation workflow. For more information, see Generate Board-Independent HDL IP Core from Simulink Model.
In the same IP core, you cannot map to both an AXI4 interface and AXI4-Lite interface.
AXi4-Lite Interface Restrictions
The inputs and outputs must have a bit width less than or equal to 32 bits.
The input and outputs must be scalar.
AXI4-Stream Video Interface Restrictions
Ports must have a 32-bit width.
Ports must be scalar.
You can have a maximum of one input video port and one output video port.
The AXI4-Stream Video interface is not supported in Coprocessing – blocking Processor/FPGA synchronization must be set to
Coprocessing – blockingmode is not supported.
Generate Board-Independent IP Core
To generate a board-independent IP core to use in an embedded system integration environment, such as Intel Qsys, Xilinx EDK, or Xilinx IP Integrator:
Create an HDL Coder™ project containing your MATLAB® design and test bench, or open an existing project.
In the HDL Workflow Advisor, define input types and perform fixed-point conversion.
To learn how to convert your design to fixed-point, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.
In the HDL Workflow Advisor, in the Select Code Generation Target task:
IP Core Generation.
Generic Xilinx Platformor
Generic Altera Platform.
Depending on your selection, the code generator automatically sets the Synthesis tool. For example, if you select
Generic Xilinx Platform, Synthesis tool automatically changes to
Additional source files: If you are using an
hdl.BlackBoxSystem object™ to include existing Verilog® or VHDL® code, enter the file names. Enter each file name manually, separated with a semicolon (
;), or by using the ... button. The source file language must match your target language.
In the Set Target Interface step, for each port, select an option from the Target Platform Interfaces drop-down list.
In the HDL Code Generation step, optionally specify code generation options, then click Run.
In the HDL Workflow Advisor message pane, click the IP core report link to view detailed documentation for your generated IP core.