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Create Software Interface Script to Control and Rapidly Prototype HDL IP Core

Rapidly prototype the HDL IP core by interfacing with your target board over Ethernet or JTAG. Use an Ethernet connection for boards that have an ARM processor. Use a JTAG connection for boards that do not have an ARM processor.

Prerequisites

Ethernet-Based Interface

To use an Ethernet-based connection to your target hardware boards that have an embedded ARM processor, you can either generate a software interface script or create a custom software script. Before setting up the Ethernet-based interface, set up the board’s SD card with the MathWorks® firmware image. To set up the firmware image for your target board:

  • For Intel® related boards, see Guided SD Card Setup (HDL Coder Support Package for Intel SoC Devices)

  • For Xilinx related boards, see Guided SD Card Setup (HDL Coder Support Package for Xilinx Zynq Platform).

Software Interface Script

When you run the Generate Software Interface task and select the Generate MATLAB software interface script check box.

The generated MATLAB files are:

    • gs_modelName_setup.m, which is a setup script that adds the AXI4 slave and AXI4-Stream interfaces. The script also contains DUT port objects that have the port name, direction, data type, and interface mapping information. The script then maps the DUT ports to the corresponding interfaces.

    • gs_modelName_interface.m, which creates a target object, instantiates the setup script gs_modelName_setup.m, and then connects to the target hardware. The script then sends read and write commands to the generated HDL IP core.

    See Generate Software Interface Script to Probe and Rapidly Prototype HDL IP Core.

    Customize the Software Interface Script

    For rapid prototyping, customize the software interface script or create your own script based on how you modify your original design. Customize the script to specify:

    • A target object for a different FPGA vendor.

    • Additional interfaces or configure existing interfaces based on modifications to your original design. HDL Coder™ uses this information to create the IIO drivers to access the HDL IP core.

    • Additional DUT port objects or remove existing objects based on how you modify your design, and then change the mapping information accordingly.

    • Input data to write to the DUT ports and output data to read from the ports.

    Develop Software Interface Script

    You can customize the generated software script or create your own software interface script. To create a custom software script:

    1. Create an fpga object for the target device and store in hFPGA.

      hFPGA = fpga("Xilinx")
      
      hFPGA = 
       
         fpga with properties:
       
               Vendor: "Xilinx"
           Interfaces: [0×0 fpgaio.interface.InterfaceBase]
          
      

      To Use an Intel target:

      hFPGA = fpga("Intel")
      
      hFPGA = 
       
         fpga with properties:
       
               Vendor: "Intel"
           Interfaces: [0×0 fpgaio.interface.InterfaceBase]
          
      

    2. Configure the AXI interfaces to map the DUT ports in the generated HDL IP core. You can add AXI4 slave and AXI4-Stream interfaces. To add AXI4 slave interfaces, use the addAXI4SlaveInterface function.

      addAXI4SlaveInterface(hFPGA, ...
      	... % Interface properties
          "InterfaceID", "AXI4-Lite", ...
          "BaseAddress", 0xA0000000, ...
          "AddressRange", 0x10000, ...
          ... % Driver properties
          "WriteDeviceName", "mwipcore0:mmwr0", ...
          "ReadDeviceName", "mwipcore0:mmrd0");
      
      

      To add AXI4-Stream interfaces, use the addAXI4StreamInterface function.

      addAXI4StreamInterface(hFPGA, ...
          ... % Interface properties
          "InterfaceID", "AXI4-Stream", ...
          "WriteEnable", true, ...
          "ReadEnable", true, ...
          "WriteFrameLength", 1024, ...
          "ReadFrameLength", 1024, ...
          ... % Driver properties
          "WriteDeviceName", "mwipcore0:mm2s0", ...
          "ReadDeviceName", "mwipcore0:s2mm0");
      
      

      The interface mapping information that you specified is saved as a property on the fpga object, hFPGA.

      hFPGA
      hFPGA = 
       
         fpga with properties:
       
               Vendor: "Xilinx"
           Interfaces: [1×2 fpgaio.interface.InterfaceBase]

      For standalone FPGA boards that do not have an embedded ARM processor, you can create an object, and then use the aximaster object. Then use this object as the driver for the addAXI4SlaveInterface function. The aximaster object requires the HDL Verifier™ support package for the Intel or Xilinx FPGA board.

      % Create an "aximaster" object 
      hAXIMDriver = aximaster("Xilinx");
      
      % Pass it into the addInterface command
      addAXI4SlaveInterface(hFPGA, ...
          ... % Interface properties
          "InterfaceID",  "AXI4-Lite", ...
          "BaseAddress",  0xB0000000, ...
          "AddressRange", 0x10000, ...
          ... % Driver properties
          "WriteDriver", hAXIMDriver, ...
          "ReadDriver", hAXIMDriver, ...
          "DriverAddressMode", "Full");
      
      

    3. Specify information about the DUT ports in the generated HDL IP core as a port object array by using the hdlcoder.DUTPort object. The object represents the ports of your DUT on the target hardware.

      hPort_h_in1 = hdlcoder.DUTPort("h_in1", ...
      	"Direction", "IN", ...
      	"DataType", numerictype(1,16,10), ...
      	"Dimension", [1 1], ...
      	"IOInterface", "AXI4-Lite", ...
      	"IOInterfaceMapping", "0x100")
      
      
      hPort_h_in1 = 
       
         DUTPort with properties:
       
                         Name: "h_in1"
                    Direction: IN
                     DataType: [1×1 embedded.numerictype]
                    Dimension: [1 1]
                  IOInterface: "AXI4-Lite"
           IOInterfaceMapping: "0x100"

      To write to or read from the DUT ports in the generated HDL IP core, map the ports to the AXI interface by using the mapPort function. After you map the ports to the interfaces, this information is saved on the fpga object as the Interfaces property.

      mapPort(hFPGA, hPort_h_in1);
      hFPGA.Interfaces
      
      
      ans = 
      
        AXI4Slave with properties:
      
            InterfaceID: "AXI4-Lite"
            BaseAddress: "0xA0000000"
           AddressRange: "0x10000"
            WriteDriver: [1×1 fpgaio.driver.AXIMemoryMappedIIOWrite]
             ReadDriver: [1×1 fpgaio.driver.AXIMemoryMappedIIORead]
             InputPorts: "h_in1"
            OutputPorts: [0×0 string]
      
      

      You can also specify this information for ports mapped to AXI4-Stream interfaces.

      hPort_x_in_data = hdlcoder.DUTPort("x_in_data", ...
      	"Direction", "IN", ...
      	"DataType", numerictype(1,16,10), ...
      	"Dimension", [1 1], ...
      	"IOInterface", "AXI4-Stream");
      
      hPort_y_out_data = hdlcoder.DUTPort("y_out_data", ...
      	"Direction", "OUT", ...
      	"DataType", numerictype(1,32,20), ...
      	"Dimension", [1 1], ...
      	"IOInterface", "AXI4-Stream");

      To write to or read from the DUT ports in the generated HDL IP core, map the ports to the AXI interface by using the mapPort function.

      mapPort(hFPGA, [hPort_x_in_data, hPort_y_out_data]);
      
      
      After you map the ports to the interfaces, this information is saved on the fpga object as the Interfaces property.
      hFPGA
      hFPGA = 
      
         fpga with properties:
       
               Vendor: "Xilinx"
           Interfaces: [1×2 fpgaio.interface.InterfaceBase]
      hFPGA.Interfaces
      ans = 
      
         AXI4Slave with properties:
       
            InterfaceID: "AXI4-Lite"
            BaseAddress: "0xA0000000"
           AddressRange: "0x10000"
            WriteDriver: [1×1 fpgaio.driver.AXIMemoryMappedIIOWrite]
             ReadDriver: [1×1 fpgaio.driver.AXIMemoryMappedIIORead]
             InputPorts: "h_in1"
            OutputPorts: [0×0 string]
       
         AXI4Stream with properties:
       
                InterfaceID: "AXI4-Stream"
                WriteEnable: 1
                 ReadEnable: 1
           WriteFrameLength: 1024
            ReadFrameLength: 1024
                WriteDriver: [1×1 fpgaio.driver.AXIStreamIIOWrite]
                 ReadDriver: [1×1 fpgaio.driver.AXIStreamIIORead]
                 InputPorts: "x_in_data"
                OutputPorts: "y_out_data"
      
      

    4. To test the HDL IP core functionality, use the readPort and writePort functions to write data to or read data from these ports.

      writePort(hFPGA, "h_in1", 5);
      
      writePort(hFPGA, "x_in", sin(linspace(0, 2*pi, 1024)));
      data = readPort(hFPGA, "y_out");
      
      
    5. After you have tested the HDL IP core, you can release the hardware resource associated with the fpga object by using the release function.

      release(hFPGA)
      
    6. For an example on creating a custom interface script and prototyping your design on a target FPGA board over an Ethernet connection, see Prototype FPGA Design on Hardware with Live Data by Using MATLAB Commands.

    JTAG Based Interface

    For standalone FPGA boards that do not have an embedded ARM processor, you can insert the JTAG MATLAB as AXI Master IP into your reference design. Create a script that uses the aximaster object that connects to the IP over a physical JTAG cable. This script enables read and write commands to slave memory locations from the MATLAB command line.

    To use MATLAB as the AXI Master:

    • Install the HDL Verifier hardware support packages.

    • Do not target standalone boards that do not have the hRD.AXI4SlaveInterface functionality or boards that are based on Xilinx ISE.

    Insert JTAG MATLAB as AXI Master

    When you run the IP Core Generation workflow, in the Set Target > Set Target Reference Design task, choose Default system for Reference Design and set Insert JTAG MATLAB as AXI Master to on.

    To generate the IP Core and create a project with AXI Master IP, right-click the Create Project task and select Run to Selected Task.

    Control the HDL Coder IP Core at the MATLAB Command Line

    You can now interact with your target FPGA board by using the JTAG MATLAB as AXI Master feature. Create an object by using the aximaster object. Use the created object as the driver for the addAXI4SlaveInterface function.

    % Create an "aximaster" object 
    hAXIMDriver = aximaster("Xilinx");
    
    % Pass it into the addInterface command
    addAXI4SlaveInterface(hFPGA, ...
        ... % Interface properties
        "InterfaceID",  "AXI4-Lite", ...
        "BaseAddress",  0xB0000000, ...
        "AddressRange", 0x10000, ...
        ... % Driver properties
        "WriteDriver", hAXIMDriver, ...
        "ReadDriver", hAXIMDriver, ...
        "DriverAddressMode", "Full");
    
    

    For an example on how to interface with a target board over JTAG, see Using JTAG MATLAB as AXI Master to control HDL Coder generated IP Core.

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