Apply RAM Mapping to Optimize Area
RAM mapping is an area optimization that maps storage and delay elements in your Simulink® model or MATLAB® code to random access memory (RAM) rather than to individual registers on hardware. RAM mapping can reduce the amount of area that your design uses in the target hardware by reducing the number of registers that elements consume and store those elements in RAM blocks.
RAM Mapping for a Simulink Model
You can map these Simulink model elements to RAM:
Delay blocks. To map delays to RAM, set the HDL block property UseRAM. For guidelines, see Map Large Delays to Block RAM.
Persistent variables in MATLAB Function blocks. To map persistent arrays in a MATLAB Function block to RAM, set the HDL block property MapPersistentVarsToRAM. For an example, see RAM Mapping With the MATLAB Function Block.
Lookup tables. To map lookup tables to RAM, set the HDL block property MapToRAM.
RAM blocks from the HDL Operations library:
Single Port RAM
Single Port RAM System
Dual Port RAM
Dual Port RAM System
Simple Dual Port RAM
Simple Dual Port RAM System
Dual Rate Dual Port RAM
Blocks with a RAM implementation.
Specify RAM Mapping for a Simulink Model
To specify RAM mapping for persistent arrays in a MATLAB Function block or Delay blocks:
Set the associated RAM mapping property for the elements that you want to map to RAM. For example, to map a Delay block to RAM, set the UseRAM HDL block property to
on. To map persistent arrays, set the MATLAB Function block HDL block property MapPersistentVarsToRAM to
Specify a minimum RAM mapping threshold by using the RAM mapping threshold configuration parameter. See RAM Mapping Parameters.
RAM Mapping for a MATLAB Design
You can map these MATLAB code elements to RAM:
Persistent array variables.
Pipeline registers in the generated HDL code.
Specify RAM Mapping for a MATLAB Design
To specify RAM mapping for delays or persistent arrays in a MATLAB function, in the Optimizations section of the HDL Code Generation tab of the MATLAB HDL Workflow Advisor:
Set the associated RAM mapping property for the elements that you want to map to RAM. For example, to map persistent arrays, select the Map persistent array variables to RAMs option. For more information, see Map Persistent Arrays and dsp.Delay Objects to RAM. To map pipelines delays to RAM, select the Map pipeline delays to RAM option.
Specify a value for the RAM mapping threshold option. For more information, see RAMThreshold.
For an example, see Map Matrices to Block RAMs to Reduce Area.
Use the RAM Mapping Threshold
When you use the configuration parameter RAM mapping threshold (bits),
you can specify a single integer to define the mapping threshold that maps
any delay or persistent array greater than that
threshold bit size to RAM. For example, if your design contains a
Delay block with a delay length of 1024 cycles and a word length
of 28 bits and you set the HDL block property UseRAM to
on and the RAM mapping threshold
256 total bits, the total RAM size of 28672 bits of
the Delay block exceeds the threshold and HDL Coder™ maps 1024x28 bits to the RAM on hardware. To calculate the total RAM
size, use this formula:
RAMSize = Delay length * Word length * Vector length * Complexity
RAMSize = Delay length * Word length = 1024*28
With a block RAM (BRAM) size on the target hardware of 1024x32 bits, the delay is mapped with 4 bits of unused width for each row of RAM. As a result, depending on the shape of the data defined by delay length and word length, RAM mapping might be inefficient.
RAM merging is a process that merges several delays and
maps them to RAM together. During HDL code generation, RAM merging occurs when
you have multiple Delay blocks with the same delay length in the
same subsystem. RAM merging fuses the delays into a single delay that has a RAM
size equal to the sum of the original RAM sizes. If this new RAM size is greater
than the RAM mapping threshold value, the merged
delays are mapped to RAM. For example, if you have three Delay
blocks in a subsystem that each have a total RAM size of 40 bits and the
RAM mapping threshold is
all three delays map to RAM because they have a total of
3x40=120 bits when they merge.
Exclude Inefficient RAM Mapping
To exclude inefficient mapping, you can specify two thresholds to define the shape of the data to map to RAM, one for delay length (for delays) or array size (for persistent array variables) and one for word length or bit width of the data type. Setting both thresholds maps delays or persistent arrays more efficiently to RAM by excluding delays or persistent arrays that inefficiently map to block RAM on the target hardware for your design. These thresholds allow you to selectively map data that has a shape similar to specific block RAM configuration on your target hardware.
Set Total RAM Size for RAM Mapping Threshold
For example, for a model with RAM Mapping Threshold set
256, both of these subsystems in the DUT in the generated
model are mapped to block RAM on the Xilinx® RAMB36E1 because both subsystems contain delays with a total bit
size of 32768 bits, which is greater than the threshold, even with different
delay lengths and bit widths.
To determine how many block RAMs are used from the design, run synthesis on the model. For more information on how to run synthesis, HDL Code Generation and FPGA Synthesis from Simulink Model.This is the Resource summary report from synthesis:
Because the BRAM on the Xilinx RAMB36E1 can be configured for both 512x64 bits and 1024x32 bits size, the first subsystem inefficiently maps to block RAM and takes up two BRAM of size 512x64 bits, while the second subsystem maps more efficiently to one BRAM of size 1024x32 bits for a total of 3 block RAM.
Set Delay Length and Word Length for RAM Mapping Threshold
For this example, the RAM Mapping Threshold is changed to
1024x1, where 1024 is the delay length threshold and 1 is
the word length threshold. To determine how many block RAMs are used, run
synthesis on the model. This is the Resource summary report from
Now, only the second subsystem is mapped to BRAM because the first subsystem has a delay length of 256 cycles, which is less than the delay length threshold of 1024. As a result, only one BRAM is used to map the second subsystem. The first subsystem is mapped to LUTs and registers.