When you partition your design into hardware and software components, use the HDL Coder™ HDL Workflow Advisor to target your design on standalone FPGA boards, SoC devices, and Speedgoat FPGA IO modules. The design consists of the DUT algorithm for which you generate the RTL code and IP core, and software components for which you generate embedded code to run on the processor. You use AXI interfaces to interface between the hardware and software components.
High-level workflow steps for targeting an SoC platform.
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you:The following synchronization modes are available:
Export, import, or configure an HDL Workflow CLI command script.
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.
How to program the target Intel or Xilinx Hardware.