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Generate SystemVerilog Code for a MATLAB Function

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This example shows how to generate SystemVerilog HDL code for MATLAB® function. SystemVerilog code has more advanced features over that Verilog® code, such as the use of array ports, package declarations, structure ports and more.

Examine Algorithm and Test Bench

This example uses a small algorithm that adds two 2-by-2 matrices of type uint8.

design_name = 'systemverilog_example';
testbench_name = 'systemverilog_example_tb';

Open the MATLAB algorithm and test bench.

open(design_name);

function out = systemverilog_example(in1, in2)
    out = in1 + in2;
end


open(testbench_name);

function systemverilog_example_tb()
    in1 = uint8([[1 2]; [3 4]]);
    in2 = uint8([[5 6]; [7 8]]);
    i = 1;
    while i < 3
        out = systemverilog_example(in1, in2);
        in1 = out;
    end
end

Create a New HDL Coder Project

To create a new project, enter the following command:

coder -hdlcoder -new systemverilog_example_prj

Under MATLAB Function, click Add MATLAB Function and select the systemverilog_example.m file. Under MATLAB Test Bench, click Add files and select systemverilog_example_tb.m.

For a more complete tutorial on creating and populating MATLAB HDL Coder projects, see Get Started with MATLAB to HDL Workflow.

Run Fixed-Point Conversion and HDL Code Generation

  1. Click Workflow Advisor to launch the Workflow Advisor in MATLAB.

  2. Click HDL Code Generation, set Language property to SystemVerilog.

  3. Right-click the HDL Code Generation task and click Run to selected task to run all the steps from the beginning through HDL code generation.

Examine the generated HDL code by clicking the links in the log window.

Generate SystemVerilog Code Using MATLAB Command Line

You can also generate SystemVerilog code for a MATLAB design by entering commands in MATLAB Command Window.

First, create a coder.config object hdlcfg.

hdlcfg = coder.config('hdl');
hdlcfg.TestBenchName = 'systemverilog_example_tb';

Set the TargetLanguage Property to SystemVerilog.

hdlcfg.TargetLanguage = 'SystemVerilog';

3. Run code generation.

codegen -config hdlcfg systemverilog_example

### Begin SystemVerilog Code Generation
### Working on systemverilog_example as <a href="matlab:edit('/tmp/Bdoc24a_2528353_2773140/tp23306d3d/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example.sv')">systemverilog_example.sv</a>.
### Generating package file <a href="matlab:edit('/tmp/Bdoc24a_2528353_2773140/tp23306d3d/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_pkg.sv')">systemverilog_example_pkg.sv</a>.
### Generating Resource Utilization Report <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc24a_2528353_2773140/tp23306d3d/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/resource_report.html')">resource_report.html</a>.
### Generating HDL Conformance Report <a href="matlab:web('/tmp/Bdoc24a_2528353_2773140/tp23306d3d/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_hdl_conformance_report.html')">systemverilog_example_hdl_conformance_report.html</a>.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
Code generation successful.

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