Generate SystemVerilog Code for a MATLAB Weighted Blend Algorithm
R2026bThis example shows how to generate synthesizable SystemVerilog HDL code from a MATLAB® function that implements a weighted blend of two images. When you generate SystemVerilog instead of Verilog®, the code generator produces array ports and package declarations that improve readability of the generated code.
Examine the Weighted-Blend Algorithm and Test Bench
In image processing pipelines, pixels are processed in small tiles. The function systemverilog_example.m implements a weighted-blend algorithm that performs an element-wise weighted blend of two 2-by-2 matrices of type uint8, corresponding to a 2-by-2 pixel tile. The function converts the inputs to uint32 for intermediate computation to avoid overflow during multiplication and accumulation.
type systemverilog_example.m
function out = systemverilog_example(in1, in2, alpha, beta) a = uint32(alpha); b = uint32(beta); x = uint32(in1); y = uint32(in2); accumulate = a .* x + b .* y + uint32(128); rescale = floor(accumulate/256); z = min(rescale, uint32(255)); out = uint8(z); end
The test bench, systemverilog_example_tb.m, tests the weighted-blend algorithm by building two different 8-by-8 test images, processing both images in 2-by-2 tiles, and comparing the result to a full-precision MATLAB reference. To process tiles, the test bench passes 2-by-2 array inputs directly to the function. This array-based interface maps to array ports in the generated SystemVerilog code.
coder.example.extractLines("systemverilog_example_tb.m","in1Blk","beta);",1,1)
in1Blk = image1(r:r+1, c:c+1);
in2Blk = image2(r:r+1, c:c+1);
outBlk = systemverilog_example(in1Blk, in2Blk, alpha, beta);
Test the Algorithm with Different Blend Weights
Run the test bench with a 50/50 weighted blend. The variables alpha and beta control how much each input image contributes to the output. When alpha and beta each equal 128, the output is an equal mix of both images.
alpha = uint8(128); beta = uint8(128); systemverilog_example_tb figure(2) tiledlayout nexttile imshow(weightedImage)
Set alpha to 25 and beta to 231 to weight the output toward the second image. The test bench reads alpha and beta from the workspace if they exist.
alpha = uint8(25); beta = uint8(231); systemverilog_example_tb nexttile imshow(weightedImage)
Generate SystemVerilog Code Using the MATLAB Command Line
To generate SystemVerilog code from the MATLAB function, create configuration objects that specify the test bench for verification and the target language for code generation.
Create a coder.FixPtConfig configuration object and set the TestBenchName property to "systemverilog_example_tb".
fixptcfg = coder.config("fixpt"); fixptcfg.TestBenchName = "systemverilog_example_tb";
Create a coder.HdlConfig object and set the TestBenchName property to "systemverilog_example_tb".
hdlcfg = coder.config("hdl"); hdlcfg.TestBenchName = "systemverilog_example_tb";
To generate SystemVerilog instead of Verilog, set the TargetLanguage property to "SystemVerilog".
hdlcfg.TargetLanguage = "SystemVerilog";
Use the codegen command to generate HDL code. Specify the fixed-point configuration with -float2fixed, the HDL configuration with -config, and the entry-point function name.
codegen -float2fixed fixptcfg -config hdlcfg systemverilog_example
===================================================
Design Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example.m')">systemverilog_example</a>
Test Bench Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example_tb.m')">systemverilog_example_tb</a>
===================================================
Input types not specified for design(s) 'systemverilog_example', inferring types by simulating the first test bench: 'systemverilog_example_tb' in the base workspace.
============= Step1: Analyze Floating-Point Code ==============
Code generation successful.
============= Step1a: Verify Floating-Point Code ==============
### Analyzing the design 'systemverilog_example'
### Analyzing the test bench(es) 'systemverilog_example_tb'
### Begin Floating-Point Simulation (Instrumented)
### Floating-Point Simulation Completed in 2.2007 sec(s)
### Elapsed Time: 3.0022 sec(s)
============= Step2: Propose Types Based on Range Information ==============
============= Step3: Generate Fixed-Point Code ==============
### Generating Fixed-Point MATLAB Code <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_fixpt.m')">systemverilog_example_fixpt</a> Using Proposed Types
### Generating Fixed-Point MATLAB Design Wrapper <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_wrapper_fixpt.m')">systemverilog_example_wrapper_fixpt</a>
### Generating Mex file for ' systemverilog_example_wrapper_fixpt '
Code generation successful: <a href="matlab: emlcprivate('emcOpenReport','/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/reports/systemverilog_example_wrapper_fixpt_mex/html/report.mldatx');">View report</a>
### Generating Type Proposal Report for 'systemverilog_example' <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_report.html', '-new')">systemverilog_example_report.html</a>
===================================================
Code generation successful.
### Begin MATLAB to HDL Code Generation...
### Working on DUT: systemverilog_example_fixpt.
### Using TestBench: systemverilog_example_tb.
### Begin SystemVerilog Code Generation
### Working on systemverilog_example_fixpt as <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt.sv')">systemverilog_example_fixpt.sv</a>.
### Generating package file <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt_pkg.sv')">systemverilog_example_fixpt_pkg.sv</a>.
### Generating Resource Utilization Report <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/resource_report.html')">resource_report.html</a>.
### Generating Optimization report
### To rerun codegen evaluate the following commands...
---------------------
cgi = load('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/codegen_info.mat');
cfg = cgi.CodeGenInfo.codegenSettings;
fxpCfg = cgi.CodeGenInfo.fxpCfg;
codegen -float2fixed fxpCfg -config cfg -report
---------------------
### Generating HDL Conformance Report <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt_hdl_conformance_report.html')">systemverilog_example_fixpt_hdl_conformance_report.html</a>.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Code generation successful: To view the report, open('codegen/systemverilog_example/hdlsrc/html/report.mldatx')
Examine the Generated SystemVerilog Code
The code generator produces two SystemVerilog files: a package file that contains shared type definitions, and the design module that uses array ports at the interface. The device under test (DUT) is the top-level design module.
View the shared type definitions in the package file. The code generator creates a typedef for each unique data type used in the MATLAB function.
file = fullfile("codegen","systemverilog_example","hdlsrc","systemverilog_example_fixpt_pkg.sv"); coder.example.extractLines(file,"package systemverilog_example_fixpt_pkg;","endpackage: systemverilog_example_fixpt_pkg",1,1)
package systemverilog_example_fixpt_pkg; typedef logic [7:0] vector_of_unsigned_logic_8; typedef logic [31:0] vector_of_unsigned_logic_32; typedef logic [23:0] vector_of_unsigned_logic_24; typedef logic [15:0] vector_of_unsigned_logic_16; typedef logic [16:0] vector_of_unsigned_logic_17; typedef logic [32:0] vector_of_unsigned_logic_33; endpackage: systemverilog_example_fixpt_pkg
View the package import and array ports in the DUT module. The 2-by-2 array inputs in1 and in2 from the MATLAB function map to array ports, preserving the tile shape at the HDL interface.
file = fullfile("codegen","systemverilog_example","hdlsrc","systemverilog_example_fixpt.sv"); coder.example.extractLines(file,"import systemverilog_example_fixpt_pkg::* ;",");",1,1)
import systemverilog_example_fixpt_pkg::* ;
( input vector_of_unsigned_logic_8 in1[0:1] [0:1] /* ufix8 [2x2] */,
input vector_of_unsigned_logic_8 in2[0:1] [0:1] /* ufix8 [2x2] */,
input logic [7:0] alpha /* ufix8 */,
input logic [7:0] beta /* ufix8 */,
output vector_of_unsigned_logic_8 out[0:1] [0:1] /* ufix8 [2x2] */);
Compare with Generated Verilog Code
To see the advantages of SystemVerilog, generate Verilog code for the same design and compare the interface.
hdlcfg.TargetLanguage = "Verilog"; codegen -float2fixed fixptcfg -config hdlcfg systemverilog_example
===================================================
Design Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example.m')">systemverilog_example</a>
Test Bench Name: <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/systemverilog_example_tb.m')">systemverilog_example_tb</a>
===================================================
Input types not specified for design(s) 'systemverilog_example', inferring types by simulating the first test bench: 'systemverilog_example_tb' in the base workspace.
============= Step1: Analyze Floating-Point Code ==============
============= Step1a: Verify Floating-Point Code ==============
### Analyzing the design 'systemverilog_example'
### Analyzing the test bench(es) 'systemverilog_example_tb'
### Begin Floating-Point Simulation (Instrumented)
### Floating-Point Simulation Completed in 1.2391 sec(s)
### Elapsed Time: 1.9078 sec(s)
============= Step2: Propose Types Based on Range Information ==============
============= Step3: Generate Fixed-Point Code ==============
### Generating Fixed-Point MATLAB Code <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_fixpt.m')">systemverilog_example_fixpt</a> Using Proposed Types
### Generating Fixed-Point MATLAB Design Wrapper <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_wrapper_fixpt.m')">systemverilog_example_wrapper_fixpt</a>
### Generating Mex file for ' systemverilog_example_wrapper_fixpt '
Code generation successful: <a href="matlab: emlcprivate('emcOpenReport','/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/reports/systemverilog_example_wrapper_fixpt_mex/html/report.mldatx');">View report</a>
### Generating Type Proposal Report for 'systemverilog_example' <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/fixpt/systemverilog_example_report.html', '-new')">systemverilog_example_report.html</a>
===================================================
Code generation successful.
### Begin MATLAB to HDL Code Generation...
### Working on DUT: systemverilog_example_fixpt.
### Using TestBench: systemverilog_example_tb.
### Begin Verilog Code Generation
### Working on systemverilog_example_fixpt as <a href="matlab:edit('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt.v')">systemverilog_example_fixpt.v</a>.
### Generating Resource Utilization Report <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/resource_report.html')">resource_report.html</a>.
### Generating Optimization report
### To rerun codegen evaluate the following commands...
---------------------
cgi = load('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/codegen_info.mat');
cfg = cgi.CodeGenInfo.codegenSettings;
fxpCfg = cgi.CodeGenInfo.fxpCfg;
codegen -float2fixed fxpCfg -config cfg -report
---------------------
### Generating HDL Conformance Report <a href="matlab:web('/tmp/Bdoc26b_3351752_3509937/tpb460897c/hdlcoder-ex49202891/codegen/systemverilog_example/hdlsrc/systemverilog_example_fixpt_hdl_conformance_report.html')">systemverilog_example_fixpt_hdl_conformance_report.html</a>.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Code generation successful: To view the report, open('codegen/systemverilog_example/hdlsrc/html/report.mldatx')
View the DUT ports in the generated Verilog file. Without SystemVerilog, the code generator flattens the 2-by-2 array inputs into individual scalar ports and does not generate a package file for shared type definitions.
file = fullfile("codegen","systemverilog_example","hdlsrc","systemverilog_example_fixpt.v"); coder.example.extractLines(file,"module systemverilog_example_fixpt",");",1,1)
module systemverilog_example_fixpt
(in1_0,
in1_1,
in1_2,
in1_3,
in2_0,
in2_1,
in2_2,
in2_3,
alpha,
beta,
out_0,
out_1,
out_2,
out_3);
To further optimize the design for target speed and area constraints, see Introduction to Optimizations in HDL Coder.
