External Memory Access

Read and write data to PL-DDR4 memory

The HDL Coder™ reference designs provide a means for your IP design to connect to programmable logic (PL) double data rate 4 (DDR4) memory interfacing by using the AXI4-Master. Capture analog-to-digital converter (ADC) data from PL-DDR4 memory and transmit waveforms out of the digital-to-analog converter (DAC) read from PL-DDR4 memory.

Featured Examples

ADC Data Capture to DDR Memory on RFSoC Device

ADC Data Capture to DDR Memory on RFSoC Device

Perform analog-to-digital converter (ADC) data captures with programmable logic (PL) double data rate 4 (DDR4) memory.

DAC Data Transmit from DDR Memory on RFSoC Device

DAC Data Transmit from DDR Memory on RFSoC Device

Transmit waveforms out of the digital-to-analog converter (DAC) that is read from programmable logic (PL) double data rate 4 (DDR4) memory. Using PL-DDR4 memory offers advantages such as the ability to access 4 gigabytes of memory space. This amount of memory can help facilitate applications requiring large waveform transmissions that are not normally feasible with FPGA block random access memory (BRAM). This figure shows the relevant intellectual property (IP) interfaces and connectivity that are used in this design.