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FIR Rate Conversion HDL Optimized

Upsample, filter, and downsample input signal and generates optimized HDL code

  • Library:
  • DSP System Toolbox HDL Support / Filtering

  • FIR Rate Conversion HDL Optimized block

Description

The FIR Rate Conversion HDL Optimized block upsamples, filters, and downsamples input signals. It is optimized for HDL code generation and operates on one sample of each channel at a time. The block implements a polyphase architecture to avoid unnecessary arithmetic operations and high intermediate sample rates.

The block upsamples the input signal by an integer factor of L, applies it to a FIR filter, and downsamples the input signal by an integer factor of M.

You can use the input and output control ports for pacing the flow of samples. In the default configuration, the block uses validIn and validOut control signals. For additional flow control, you can enable a ready output signal and a request input signal.

The ready output port indicates that the block can accept a new input data sample on the next time step. When LM, you can use the ready signal to achieve continuous output data samples. If you apply a new input sample after each time the block returns ready signal as 1, the block returns a data output sample with the validOut signal set to 1 on every time step.

When you disable the ready port, you can apply a valid data sample only every ceil(L/M) time steps. For example, if:

  • L/M = 4/5, then you can apply a new input sample on every time step.

  • L/M = 3/2, then you can apply a new input sample on every other time step.

When you enable the request input port, the block returns the next output sample when therequest signal is 1 and a valid output sample is available. When you disable the request port, the block returns output samples when they are available. When no new data is available, block sets the validOut signal to 0.

You can connect the request input port to the ready output port of a downstream block.

Ports

Input

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Input data sample, specified as a scalar, or as a row vector in which each element represents an independent channel. The block accepts real or complex data.

double and single data types are supported for simulation, but not for HDL code generation.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

When valid is 1 (true), the block captures the data from the dataIn port. You can apply a valid data sample every ceiling(L/M) time steps.

Data Types: Boolean

When the request port is 1, and an output data sample is available, the block returns that output data sample on the dataOut port and sets the validOut output signal to 1. When no new data is available, the block sets the validOut output signal to 0. When the request port is 0, the block holds available data until the request port is set to 1.

You can connect the request input port to the ready output port of a downstream block.

Dependencies

To enable this port, select the Enable request input port checkbox.

Data Types: Boolean

Output

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Output data sample, returned as a scalar or a row vector in which each element represents an independent channel.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

The block sets validOut to true along with each valid data returned on the dataOut output port.

Data Types: Boolean

The block sets ready to true to indicate that it is ready for new input data on the next cycle.

You can connect the ready output port to the request input port of an upstream block.

Dependencies

To enable this port, select the Enable ready output port checkbox.

Data Types: Boolean

Parameters

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Main

Specify a factor by which the block interpolates the input data sample.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Specify a factor by which the block decimates the input data sample.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Specify a row vector of coefficients in descending powers of z-1.

Note

You can generate filter coefficients using Signal Processing Toolbox™ filter design functions (such as fir1). Design a lowpass filter with normalized cutoff frequency no greater than min(1/L,1/M). The block initializes internal filter states to zero.

Control Ports

Select this parameter to enable the ready port.

Select this parameter to enable the request port.

Data Types

Select a rounding mode for fixed-point operations. For more information, see Rounding mode.

Specify whether overflows saturate or wrap.

  • off — Overflows wrap to the appropriate value that data type can represent. For example, because 130 does not fit in a signed 8-bit integer, it wraps to -126.

  • on — Overflows saturate to either the minimum or maximum value that data type can represent. For example, an overflow associated with a signed 8-bit integer can saturate to -128 or 127.

FIR filter coefficients data type, specified as a fixdt(s,wl,fl) object with signedness, word length, and fractional length properties.

Specify the data type for the output data samples.

Algorithms

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The FIR Rate Conversion HDL Optimized block implements a fully parallel polyphase filter architecture. The diagram shows where the block casts the data types based on your configuration.

Extended Capabilities

Introduced in R2015b