Decimate signal using cascaded integratorcomb filter optimized for HDL code generation
DSP System Toolbox HDL Support / Filtering
The CIC Decimation HDL Optimized block decimates an input signal by using a cascaded integratorcomb (CIC) decimation filter. CIC filters are a class of linear phase FIR filters consisting of a comb part and an integrator part. The CIC decimation filter structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters. For more information about CIC Decimation filter, see Algorithms.
The block supports both fixed and variable decimation rates. It provides an architecture suitable for HDL code generation and hardware deployment.
data
— Input dataInput data, specified as a signed integer or signed fixed point with a word length less than or equal to 32.
Data Types: int8
 int16
 int32
 fixed point
Complex Number Support: Yes
valid
— Indication of valid input dataIndication of valid input data, specified as a Boolean scalar.
This port is a control signal that indicates if the input data is valid. When this
value is 1
, the block captures the values from the
data input port. When this value is 0
, the
block ignores the values from the data input port.
Data Types: Boolean
decimFactor
— Variable decimation rate2
(default)  scalar from 2 to 2048Use this port to dynamically specify the variable decimation rate during run time.
This value must be of data type ufix12
and in the range from 2
to the Decimation factor (R) parameter value.
To enable this port, select the Variable decimation parameter.
Data Types: fixdt(0,12,0)
reset
— Clear internal statesClear internal states, specified as a Boolean scalar.
When this value is 1
, the block stops the current calculation
and clears all internal states. When this value is 0
and the input
valid is 1
, the block starts a new filtering
operation.
To enable this port, select the Enable reset input port parameter.
Data Types: Boolean
data
— CIC decimated output dataCIC decimated output data, returned as a scalar.
You can define the output data type of the block by setting the Output data type parameter.
Data Types: int8
 int16
 int32
 fixed point
Complex Number Support: Yes
valid
— Indication of valid output dataIndication of valid input data, returned as a Boolean scalar.
This port is a control signal that indicates if the data from the
data output port is valid. When this value is
1
, the block returns valid data on the data
output port. When this value is 0
, the values on the
data output port are not valid.
Data Types: Boolean
Variable decimation
— Variable decimation rateoff
(default)  on
Select this parameter to operate the block with a variable decimation rate specified from the decimFactor port. Clear this parameter to operate the block with a fixed decimation rate specified from the Decimation factor (R) parameter.
Decimation factor (R)
— Decimation factor2
(default)  integer from 2 to 2048Specify the decimation factor rate with which you want to decimate the input.
Set this parameter to the maximum possible value supported from the decimFactor port, when you select the Variable decimation parameter.
Differential delay (M)
— Differential delay1
(default)  2
Specify the differential delay of the comb part of the block.
Number of sections (N)
— Number of integrator and comb sections2
(default)  1
 3
 4
 5
 6
Specify the number of sections in either the comb part or the integrator part of the block.
Output data type
— Data type of outputFull precision
(default)  Same word length as input
 Minimum section word lengths
Select the data type for the output data.
Full precision
— The output data type has a
word length equal to the input word length plus gain bits.
Same word length as input
— The output data
type has a word length equal to the input word length.
Minimum section word lengths
— The output data
type uses the word length you specify in the Output word length
parameter. When you select this option, the block applies the Pruning algorithm.
For more information about the Pruning algorithm, see [1]. This option is not
supported when you select the Variable decimation
parameter.
Output word length
— Word length of output16
(default)  integer from 2 to 104Specify the word length of the output.
When this value is 2
,
3
, 4
, 5
, or
6
the block might overflow the output data.
To enable this parameter, set the Output data type parameter
to Minimum section word lengths
.
Gain correction
— Output gain compensationoff
(default)  on
Select this parameter to compensate for the output gain of the block.
Depending on the type of decimation you specify and the value of this parameter, the latency of the block changes.
For fixed decimation (the Variable decimation parameter is cleared):
When you clear this parameter, the latency of the block is 3 + N clock cycles.
When you select this parameter, the latency of the block is 3 + N + 9 clock cycles.
For variable decimation (the Variable decimation parameter is selected):
When you clear this parameter, the latency of the block is 4 + N clock cycles.
When you select this parameter, the latency of the block is 4 + N + 9 clock cycles.
Enable reset input port
— Reset signaloff
(default)  on
Select this parameter to enable the reset input port.
The transfer function of a CIC decimation filter is
$$H(z)={\left[{\displaystyle \sum _{k=0}^{RM1}{z}^{k}}\right]}^{N}=\frac{{\left(1{z}^{RM}\right)}^{N}}{{\left(1{z}^{1}\right)}^{N}}=\frac{1}{{\left(1{z}^{1}\right)}^{N}}\xb7\frac{{\left(1{z}^{RM}\right)}^{N}}{1}={H}_{\text{I}}{}^{N}(z)\xb7{H}_{\text{c}}{}^{N}(z),$$
where:
H_{I} is the transfer function of the integrator part of the filter.
H_{C} is the transfer function of the comb part of the filter.
N is the number of sections. The number of sections in a CIC filter is defined as the number of sections in either the comb part or the integrator part of the filter. This value does not represent the total number of sections throughout the entire filter.
R is the decimation factor.
M is the differential delay.
The CIC Decimation HDL Optimized block has the CIC filter structure shown in this figure. The structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters [1].
You can locate the unit delay in the integrator part of the CIC Filter in either the feedforward or feedback path. These two configurations yield an identical filter frequency response. However, the numerical outputs from these two configurations are different due to the latency of the block. Because, the configuration is preferred for HDL implementation, this block puts the unit delay in the feedforward path of the integrator.
The block downsamples the integrator stage output using R, either the fixed decimation rate provided using the Decimation factor (R) parameter or the variable decimation rate provided using the decimFactor input port. At the downsampler stage, the block uses a counter to count the valid input samples, which depend on the decimation rate. Whenever the decimation rate changes, the block resets and starts a new calculation from the next sample. This mechanism prevents the block from accumulating false values. Then, the block provides the decimated output to the comb part.
The gain of the block is given by $$Gain={(R\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{x}\text{\hspace{0.17em}}M)}^{N}$$,
where:
R is the Decimation factor (R) parameter value.
M is the Differential delay (M) parameter value.
N is the Number of sections (N) parameter value.
The block implements gain correction in two parts: coarse gain and fine gain. In coarse gain correction, the block calculates the shift value, adds the shift value to the fractional bits to create a numeric type, and performs a bitshift left and reinterpretcast. In fine gain correction, the block divides the remaining gain with the coarse gain if the gain is not a power of 2. Then, the block multiplies the corrected coarse gain corrected value with the inverse value of the fine gain. Before the block starts processing, all possible shift and fine gain values are precalculated initially and stored in an array.
You can modify this equation as $$Gain={2}^{cGain}\text{\hspace{0.17em}}\text{x}\text{\hspace{0.17em}}\text{\hspace{0.17em}}fGain$$. In this equation, cGain is the coarse gain, and fGain is the fine gain. These gains are given by these equations.
$$cGain=floor({\mathrm{log}}_{2}Gain)$$
$$fGain=Gain/{2}^{cGain}=Gain\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{x}\text{\hspace{0.17em}}\text{\hspace{0.17em}}{2}^{cGain}{}^{}$$
To perform gain correction when the Variable decimation parameter is selected, the block sets the output data type configured with the maximum decimation rate and bitshifts left for all the values under the maximum decimation rate. The bitshift value is equal to $${\text{Maximumgainlog}}_{\text{2}}\text{(currentgain)}$$.
This section explains how the block outputs data based on the output data type selection. Consider a block with R, M, and N values 8, 1, and 3, respectively, and an input width of 16. The output word length is calculated as $${B}_{\text{OUT}}=\text{\hspace{0.17em}}\text{\hspace{0.17em}}{B}_{\text{IN}}+\text{\hspace{0.17em}}\text{\hspace{0.17em}}[{\mathrm{log}}_{2}(Gain)]$$,
where:
$$Gain={(R\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{x}\text{\hspace{0.17em}}M)}^{N}$$
B_{IN} is the input word length.
B_{OUT} is the output word length.
When you set the Output data type parameter to Full
precision
, the block outputs data with a word length of 25 by adding nine
gain bits to the input word length of 16.
When you set the Output data type parameter to Same
word length as input
, the block outputs data with a word length of 16, which
is the same length as the input word length. The internal integrator and comb stages use the
fullprecision data type with 25 bits.
When you set the Output data type parameter to Minimum
section word lengths
and the Output word length
parameter to 16
, the block outputs data with a word length of 16. In this
case, the block changes the bit width at each stage, based on the Pruning algorithm.
If the Output word length parameter value is less than the number of bits required at the block output, the least significant bits (LSBs) at the earlier stages are pruned. The number of LSBs to discard at each stage is provided in the Hogenauer algorithm [1]. This algorithm minimizes the loss of information in the output data.
This section shows the latencies of the block when operated with fixed and variable decimation rates.
This figure shows the output of the block for the default configuration, that is, a
fixed decimation rate with R, M, and
N values 2, 1, and 2, respectively. The block returns valid output data
at every second cycle based on the fixed Decimation factor (R) value of
2
. The latency of the block is 5 clock cycles, and is calculated as 3 +
N.
This figure shows the output of the block for a fixed decimation with
R, M, and N values 8, 1, and 3,
respectively, and with the Gain correction parameter selected. The
block returns valid output data at every eighth cycle based on the fixed
Decimation factor (R) value of 8
. The latency of
the block is 15 clock cycles, and is calculated as 3 + N + 9.
This figure shows the output of the block for variable decimation
(decimFactor) input port values 2, 4, and 8 and M
and N values 1 and 3, respectively. In this case, the Gain
correction parameter is cleared. The block returns valid output data at second,
fourth, and eight cycles corresponding to the decimFactor port values
2
, 4
, and 8
, respectively. The
block accepts decimFactor port value changes only when the
valid input port is 1
.The latency of the block is
7 clock cycles, and is calculated as 4 + N.
The performance of the synthesized HDL code varies with your target and synthesis options. This table shows the resource and performance data synthesis results of the block with fixed and variable decimation rates when R, M, and N values are 2, 1, and 2, respectively. The generated HDL is targeted to a Xilinx^{®} Zynq^{®} 7000 ZC706 evaluation board.
Decimation Type  Slice LUTs  Slice Registers  Maximum Frequency in MHz 

Fixed rate  101  166  711.74 
Variable rate  206  186  441.70 
Resources and frequencies vary based on R, M, and N values and other parameter values selected in the block mask.
[1] Hogenauer, E. “An Economical Class of Digital Filters for Decimation and Interpolation.” IEEE Transactions on Acoustics, Speech and Signal Processing vol. 29, no. 2, Apr. 1981, pp. 155–162.
This block supports C/C++ code generation for Simulink^{®} accelerator and rapid accelerator modes and for DPI component generation.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

dsp.CICCompensationDecimator
 dsp.CICCompensationInterpolator
 dsp.CICDecimator
 dsp.CICInterpolator
 dsp.HDLCICDecimation
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