A phase-locked loop combines a voltage-controlled oscillator and a phase comparator as a feedback system to adjust the oscillator frequency or phase to track an applied frequency-modulated or phase-modulated signal.
A voltage-controlled oscillator is one part of a phase-locked loop. The Continuous-Time VCO and Discrete-Time VCO blocks implement voltage-controlled oscillators. These blocks produce continuous-time and discrete-time output signals, respectively. Each block's output signal is sinusoidal, and changes its frequency in response to the amplitude variations of the input signal.
A phase-locked loop (PLL), when used in conjunction with other components, helps synchronize the receiver. A PLL is an automatic control system that adjusts the phase of a local signal to match the phase of the received signal. The PLL design works best for narrowband signals.
A simple PLL consists of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). For example, the following figure shows how these components are arranged for an analog passband PLL. In this case, the phase detector is just a multiplier. The signal e(t) is often called the error signal.
This table indicates the supported types of PLLs and the blocks that implement them.
Supported PLLs in Components Library
Different PLLs use different phase detectors, filters, and VCO characteristics. Some of these attributes are built into the PLL blocks in this product, while others depend on parameters that you set in the block mask:
You specify the filter's transfer function in the block mask using the
Lowpass filter numerator and Lowpass
filter denominator parameters. Each of these parameters is a
vector that lists the coefficients of the respective polynomial in order of
descending exponents of the variable s. To design a
filter, you can use functions such as
cheby2 in Signal Processing
You specify the key VCO characteristics in the block mask. All four PLL blocks use a VCO input sensitivity parameter. Some blocks also use VCO quiescent frequency, VCO initial phase, and VCO output amplitude parameters.
The phase detector for each of the PLL blocks is a feature that you cannot change from the block mask.
Unlike passband models for a phase-locked loop, a baseband model does not depend on a carrier frequency. This allows you to use a lower sampling rate in the simulation. Two blocks implement analog baseband PLLs:
The linearized model and the nonlinearized model differ in that the linearized model uses the approximation
to simplify the computations. This approximation is close when Δθ(t) is near zero. Thus, instead of using the input signal and the VCO output signal directly, the linearized PLL model uses only their phases.
The charge pump PLL is a classical digital PLL. Unlike the analog PLLs mentioned above, the charge pump PLL uses a sequential logic phase detector, which is also known as a digital phase detector or a phase/frequency detector.
 Gardner, F.M., “Charge-pump Phase-lock Loops,” IEEE Trans. on Communications, Vol. 28, November 1980, pp. 1849–1858.
 Gardner, F.M., “Phase Accuracy of Charge Pump PLLs,” IEEE Trans. on Communications, Vol. 30, October 1982, pp. 2362–2363.
 Gupta, S.C., “Phase Locked Loops,” Proceedings of the IEEE, Vol. 63, February 1975, pp. 291–306.
 Lindsay, W.C. and C.M. Chie, “A Survey on Digital Phase-Locked Loops,” Proceedings of the IEEE, Vol. 69, April 1981, pp. 410–431.
 Mengali, Umberto, and Aldo N. D'Andrea, Synchronization Techniques for Digital Receivers, New York, Plenum Press, 1997.
 Meyr, Heinrich, and Gerd Ascheid, Synchronization in Digital Communications, Vol. 1, New York, John Wiley & Sons, 1990.
 Moeneclaey, Marc, and Geert de Jonghe, “ML-Oriented NDA Carrier Synchronization for General Rotationally Symmetric Signal Constellations,” IEEE Transactions on Communications, Vol. 42, No. 8, Aug. 1994, pp. 2531–2533.
 Rice, Michael. Digital Communications: A Discrete-Time Approach. Upper Saddle River, NJ: Prentice Hall, 2009.