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HDL Verifier

FPGA-in-the-Loop for Control Applications

FPGA-in-the-Loop for Control Applications

Return a larger output data size when using an overclocking factor

FPGA-in-the-Loop Custom Clock Speed

FPGA-in-the-Loop Custom Clock Speed

Specify the FPGA system clock frequency in the FIL Wizard

Multirate SystemVerilog DPI Components

Multirate SystemVerilog DPI Components

Generate multirate test benches to verify that your generated component matches Simulink behavior

Logic Analyzer

Logic Analyzer

Visualize, measure, and analyze transitions and states over time for Simulink signals (requires DSP System Toolbox)

Watch video02:51

PCI Express FPGA-in-the-Loop

PCI Express FPGA-in-the-Loop

Perform FIL simulation on selected Xilinx and Altera development boards

Watch video02:52

Watch video02:52

Latest Releases

R2016b (Version 5.1) - 14 Sep 2016

Version 5.1, part of Release 2016b, includes the following enhancements:

  • FPGA Data Capture: Probe internal FPGA signals to analyze in MATLAB or Simulink
  • FPGA-in-the-Loop for Control Applications: Return a larger output data size when using an overclocking factor
  • FPGA-in-the-Loop Custom Clock Speed: Specify the FPGA system clock frequency in the FIL Wizard
  • Multirate SystemVerilog DPI Components: Generate multirate test benches to verify that your generated component matches Simulink behavior
  • Logic Analyzer: Visualize, measure, and analyze transitions and states over time for Simulink signals (requires DSP System Toolbox)

See the Release Notes for details.

R2016a (Version 5.0) - 3 Mar 2016

Version 5.0, part of Release 2016a, includes the following enhancements:

  • PCI Express FPGA-in-the-Loop: Perform FIL simulation on selected Xilinx and Altera development boards
  • Faster Test Bench Generation and HDL Simulation: Generate SystemVerilog DPI test benches for large data sets from HDL Coder
  • Expanded Data Type Support in SystemVerilog DPI: Generate SystemVerilog DPI components for models that have buses, structures, or complex signals as I/O
  • Additional FPGA Board Support: Perform FPGA-in-the-loop simulation with Xilinx Kintex UltraScale and Altera MAX 10 family boards

See the Release Notes for details.

R2015b (Version 4.7) - 3 Sep 2015

Version 4.7, part of Release 2015b, includes the following enhancements:

See the Release Notes for details.

R2015a (Version 4.6) - 5 Mar 2015

Version 4.6, part of Release 2015a, includes the following enhancements:

  • FPGA-in-the-loop through JTAG for Xilinx boards
  • FPGA-in-the-Loop support for rapid accelerator mode in Simulink
  • DPI-C enhancements, including multiple-instance support and integration with build toolchain
  • IP-XACT support for TLM

See the Release Notes for details.

R2014b (Version 4.5) - 2 Oct 2014

Version 4.5, part of Release 2014b, includes the following enhancements:

  • SystemVerilog DPI-C component generation based on MATLAB Coder
  • SystemVerilog DPI-C component generation based on Simulink Coder
  • Xilinx Vivado support for FPGA-in-the-Loop

See the Release Notes for details.